Christos John Georgiou

Gain equalization in metropolitan and wide area optical networks using optical amplifiers

Optical metropolitan/wide area networks with arbitrary topology usually require optical amplifiers to compensate for the fiber attenuation and splitting loss introduced by the star couplers. An amplifier placement algorithm using spanning tree traversal is proposed. Using this algorithm, the authors show that it is possible to equalize the arriving optical signals at each receiver of the network. This technique enhances other static or dynamic gain equalization schemes and presents a more effective and robust solution to the power equalization problem for WDMA networks with arbitrary topology.<<ETX>>

Scalable protocol engine for high-bandwidth communications

We have proposed and evaluated a scalable architecture for implementing multi-gigabit protocol engines. The architecture utilizes a combination of custom-made VLSI circuitry and a general-purpose processor, such as the Intel 960 or the IBM PowerPC 403. Time critical operations such as line coding/decoding, CRC generation/checking, context-independent header processing, and buffer management are implemented in the customized VLSI part. These designs are never-the-less scalable and can be cascaded to further increase throughput. Some of the packet level processing, such as context-dependent header processing, are performed by the general-purpose processor. As processing power increases, more and more functions can be included in the general purpose processor. The throughput of this architecture is shown to be adequate for the operations and bit rates currently specified by Fibre Channel. Future CMOS technology advances will have the potential to further improve the raw throughput.

The IBM Enterprise Systems Connection (ESCON) Director: a dynamic switch for 200Mb/s fiber optic links

This paper describes the function and hardware structure of the Enterprise Systems Connection (ESCON™) Director™, an I/O switch capable of providing dynamic, nonblocking, any-to-any connectivity for up to 60 fiber optic links operating at 200 Mb/s. Optoelectronic conversion at the switch ports allows the switching of the fiber optic links to be done electronically. The establishment of paths in the switching matrix is done by means of a hard-wired, pipelined controller at a maximum rate of five million connections/disconnections per second. Routing information is provided in the header of data frames. The switch-port function, switching matrix, and matrix controller were implemented in the IBM 1-µm CMOS “standard cell” technology. The paper discusses the system interconnection philosophy, details of the data flow, the switch hardware architecture, the design methodology, and the approach to technology implementation.

Strategies for accelerating the worldwide adoption of e-commerce

In recent years, many organizations have recognized the potential of e-commerce to improve profitability by increasing productivity and market penetration while reducing costs. But the vision of an electronically interconnected world requires the global adoption of e-commerce, not just in industrialized nations, but also in developing ones, where most of worlds population lives. To successfully encourage the embrace of the Internet and e-commerce, one must carefully study the unique socioeconomic and cultural aspects of such nations. This article discusses ways to stimulate the worldwide adoption of e-commerce, based on our case study of Greece, a nation that has been slow to embrace Internet technologies.

Chapter 2 – A Programmable, Scalable Platform for Next-Generation Networking

Publisher Summary This chapter describes a scalable parallel network processor architecture for handling next-generation storage networking at line speeds of 10 Gb/s or higher. By using many simple, but general-purpose processors and embedded memory, high levels of processing power per mm2 of silicon area can be achieved, making this architecture ideally suited to the computationally intensive conversion of protocols required by current and emerging storage networks. The coarse-grain parallelization of protocol tasks and synchronization via queues and message passing are a good match for the parallel processor core environment. Simulations show that a chip with fewer than 16 processor cores can easily handle the protocol conversion between 10 Gb/s Fibre Channel and Infiniband networks. Larger configurations are used for the implementation of small computer systems interface protocols.

Reliable design of large crosspoint switching networks

A major source of transient errors and unreliable operation of large crosspoint switching networks is the simultaneous switching ( Delta I) noise that is caused by the switching of a large number of off-chip drivers in a chip. An architectural solution to this problem is presented for networks constructed from one-sided crosspoint switching chips. The method seeks to achieve a uniform distribution of active drivers among the chips by rearranging a subset of the existing connections when a new connection is made. The problem is studied in the context of a one-sided crosspoint network with N=rn ports constructed from individual switching chips of size n*m/2. The authors show that the lower bound of m/r active drivers per chip can always be maintained in practice when m/r is an even number. The maximum number of rearrangements needed is min(m/2-1, 2r-1). In addition, the rearrangements are confined to two chip columns of the matrix.<<ETX>>

Multipath hierarchies in interconnection networks

In this paper we presented a new approach to interconnection networks for high-performance multiprocessor systems. First, we examined the functions performed by interconnection networks, in general, and identified the delays that are limiting factors to the performance of conventional multistage networks. Then we proposed a network structure which optimizes the delays of each network function, by separating the control flow from the data flow and transmitting the control information through a hierarchy of physical paths with varying transfer speeds. We showed that the control hierarchy could be implemented by using fast networks provided by crossbars and slower networks provided by Δ-nets. Finally, we presented the results of a feasibility study, which showed that the hierarchical control networks are realizable with current VLSI technology.

Implementation and performance analysis of congestion-tolerant isochronous communication in ATM networks using diversified routing

Packet loss resulting from transient traffic congestion or hardware component failures has been a potential problem for existing ATM networks that support isochronous traffic. Packet retransmission is usually less effective in an isochronous environment due to its timing requirements. The implementation and performance of a space diversified approach for establishing isochronous interconnection is studied in this paper. In this scheme, a packet is either replicated or split into smaller packets with parity packets and sent through physically disjoint connections. By providing either partial or full redundant connections through a network, the probability of transmitting a packet that meets the jitter requirement can be increased for the same jitter bound, or a more stringent jitter bound can be imposed for the same packet loss probability.<<ETX>>

Rearrangeable operation of large crosspoint switching networks

A major impediment to building large crosspoint chips for configuring crosspoint switching networks is the simultaneous switching (Delta-I) noise problem that is caused by the switching of a large number of line drivers driving the output pins of the package. This limits the size of the largest crosspoint chips that can be operated reliably. An architectural solution to this problem is presented for networks constructed from one-sided crosspoint switching chips. The approach seeks to minimize the maximum number of active drivers in the individual chips by distributing the active drivers in the network uniformly among the chips by allowing rearrangements of existing connections when a new connection is made. A graph model is used to determine the number and location of rearrangements. An allocation scheme based on a simplified graph model that achieves a 50% reduction in the maximum number of active drivers per chip as compared to a random allocation strategy is presented. A maximum of three rearrangements is sufficient to obtain this reduction. >

Enhancement of token bus protocols for multimedia applications

The authors describe a method to enhance the medium access control (MAC) function of shared resource networks, such as buses. A new addressing field is introduced in the transmitted frames that allows multiple token visits in the same node within a single token rotation cycle. This method provides the capability to efficiently support dynamic bandwidth allocation and, thus, implement isochronous communications.<<ETX>>