Marcel Balaz

MDCT IP Core Generator with Architectural Model Simulation

Compression of digital audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and digital signal processors. Several compression schemes were developed and well established. Most of them adopt MDCT/IMDCT. This paper presents a new MDCT IP core generator. The software tool generates several MDCT architectures with adjustable parameters for FPGA-based design as well as computation precision and area estimations

Generic Self Repair Architecture with Multiple Fault Handling Capability

Built-in self-repair (BISR) approach utilized mostly in regular structures of memory cores has been a promising approach to increase the reliability of any type of integrated circuit. BISR considers spare blocks which in the case of a fault occurrence are used to replace defected circuit parts. A new fault detection and repair procedure with a generic BISR architecture for logic cores is presented in this paper. The architecture is able to localize and repair multiple faults (both permanent and transient), to identify faulty functional blocks, to detect faulty backup blocks, and to repair the core function by employing backup blocks if possible. The number of repairable faults is determined by the number of reconfigurable logic blocks (RLBs) in the core. The whole repair procedure needs only 4 test runs. Experimental results show an additional area of approximately 140% which is still within acceptable level compared to other redundant methods (TMR overhead is 200% without the voter area).

SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults

The continuous trend to decrease the cost-per-function and to increase the quality of integrated circuits amplifies the test challenges. Overall low production cost can be achieved only by considering the test area overhead, the test application time and the test quality. The fulfillment of these requirements is possible by application of short tests, use of low-overhead design-for-testability methods/standards and targeting more realistic fault models. The satisfiability-based test pattern generator of compressed skewed-load tests for transition delay faults is proposed. The test application is possible to logic cores of systems-on-chip even with only one storage element per cell in the wrapper boundary register and in the internal scan chain. Therefore, the test area is kept low while the testability of delay faults is ensured. The proposed method represents a new efficient approach for generating compressed skewed-load tests. The experimental results show significant test length reduction and increased fault coverage.

MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio

MDCT is the basic processing component for high quality audio compression. It is also the most computationally intensive operation in the vast majority of audio compression standards. Mostly used audio standard for audio compression is still MP3. This paper presents new implementations of five MDCT / IMDCT architectures with different parallelization levels for MP3. Implementation utilize UMC 90 nm CMOS technology. Design was optimized for low power applications. Low power libraries and clock gating technique were used for power reduction. All IP cores are capable of computing forward and backward MDCT and this feature makes them universal in multimedia SoCs for accelerating the MP3 audio compression/decompression.

Generic built-in self-repair architectures for SoC logic cores

The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of system-on-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure.

Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores

Built-in self-repair (BISR) architectures and methods are widely used for memory cores of system-on-chips (SoCs), where the area-efficient fault detection and repair are crucial in order to meet the high quality requirements. Research of BISR architectures for logic cores has begun as well. However, the irregular structure of logic cores represents a serious limitation and therefore, currently only ad hoc methods exist. Automated generation of BISR architectures for random logic SoC cores is proposed in this paper. The generation is guided by the characteristics of the architecture: mean time to failure (MTTF) and area overhead. The main contribution is the fully automated handling of arbitrary random logic cores and the possibility to generate architectures based on various BISR principles. The proposed method was implemented and evaluated over benchmark circuits, and the experiments confirmed that BISR architectures can be successfully generated for random logic cores. The MTTFs of the generated architectures have been improved at the cost of relatively low area overhead.

SAT-based generation of compressed skewed-load tests for transition delay faults

Skewed-load tests ensure application of delay tests to logic cores of system-on-chip with only one storage element per cell in the wrapper boundary register and in the internal scan chain. This resolves the test area problem but the fault coverage and the test application time still require optimization efforts. The satisfiability-based test pattern generator of compressed skewed-load tests for transition delay fault is proposed. It represents a new efficient approach for generating compressed skewed-load tests because the test is gradually generated without the need of a pre-generated set of initialization and excitation vectors. Two optimization methods are also proposed. The first method, the wrapper cell ordering method, increases the fault coverage by reducing the shift dependence of skewed-load tests. The second method, the fault ordering method, ensures shorter tests by determining the order in which the faults will be targeted during the test generation and consequently, the new test vectors can overlap the test sequence in the greatest degree. The proposed methods were evaluated over benchmark circuits and the experimental results show higher fault coverages and shorter test lengths.

SfW method: Delay test generation for simple chain wrapper architecture

The aim of the presented work is to improve the quality of testing of SoC digital cores surrounded with test wrappers. The paper presents a new effective delay fault test generation method for the transition faults based on the skewed-load test. The generated delay fault test can be applied to a SoC core through a test wrapper architecture with only a simple boundary scan chain. This eliminates the necessity to use an enhanced boundary scan chain for the application of the delay fault test. The effectiveness of the developed method for a transition delay test generation was verified on the set of combinational and sequential circuits. The experiments show a significant reduction of test vector application time.

An Improved MDCT IP Core Generator with Architectural Model Simulation

Compression of digital audio signals has become very important audio computation process. When audio data are compressed it is possible to store more data in a smaller memory and to increase the overall audio data throughput transferred through an interface. Several compression schemes were developed and well established. Most of them adopt the MDCT/IMDCT. This paper presents an software tool, an improved MDCT IP core generator with architectural model simulation that is capable to generate several MDCT architectures with adjustable parameters for FPGA-based design. The software tool has integrated functions of the computation precision and area estimation, which facilitate and speed up the design process.

FPGA Implementation of a Fast MDCT Algorithm

Compression of digital audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and DSPs. Several compression schemes were developed. Most of them adopt the MDCT/IMDCT. This paper presents a FPGA implementation of a fast MDCT algorithm. An investigation of different approaches of implementation and usage of standard embedded FPGA elements for specific digital signal processing has been carried out. The two designs presented in this paper are suitable for real-time applications of multi-channel audio digital signal processing