Martin Simlastik

Clockless Implementation of LEON2 for Low-Power Applications

Vower consumption has become increasingly more important with the advent mobile and wireless devices. This paper presents a clockless implementation of LEON2 processor IP core as a possible solution to the reduction of the processor power consumption. The de-synchronization methodology can be considered as a fast and efficient way to convert synchronous circuits into asynchronous ones. The design flow that is used for the de-synchronization works with a synthesizable HDL specification of the circuit, using the conventional synchronous HDL constructs. Standard synchronous design tools can be used, however, in a more elaborate way. The de-synchronized LEON2 processor could provide a low power, low EMI, clock-jitter-free and clock-skew-free solution of a full featured opensource 32-bit processor.

MDCT IP Core Generator with Architectural Model Simulation

Compression of digital audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and digital signal processors. Several compression schemes were developed and well established. Most of them adopt MDCT/IMDCT. This paper presents a new MDCT IP core generator. The software tool generates several MDCT architectures with adjustable parameters for FPGA-based design as well as computation precision and area estimations

Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey

Automated synchronous-to-asynchronous circuit conversion can be considered as one area of clockless design style, which is becoming more and more interesting for synchronous designers with lack of knowledge and experience in the real asynchronous circuit design. Another reason why it is becoming so interesting is that the languages and design styles for specification of asynchronous circuits require a learning curve to understand, become proficient with them, and to use them effectively. Hence, numerous approaches for automated conversion of synchronous circuits into their asynchronous counterparts have been proposed in recent years. The main reason is the exploitation of the often claimed advantages of asynchronous circuits, especially their lower power consumption. This paper surveys some of the available well-known synchronous-to-asynchronous conversion techniques and tries to present both their positive and negative properties.

An Improved MDCT IP Core Generator with Architectural Model Simulation

Compression of digital audio signals has become very important audio computation process. When audio data are compressed it is possible to store more data in a smaller memory and to increase the overall audio data throughput transferred through an interface. Several compression schemes were developed and well established. Most of them adopt the MDCT/IMDCT. This paper presents an software tool, an improved MDCT IP core generator with architectural model simulation that is capable to generate several MDCT architectures with adjustable parameters for FPGA-based design. The software tool has integrated functions of the computation precision and area estimation, which facilitate and speed up the design process.

FPGA Implementation of a Fast MDCT Algorithm

Compression of digital audio signals has become increasingly more important with the advent of fast and inexpensive microprocessors and DSPs. Several compression schemes were developed. Most of them adopt the MDCT/IMDCT. This paper presents a FPGA implementation of a fast MDCT algorithm. An investigation of different approaches of implementation and usage of standard embedded FPGA elements for specific digital signal processing has been carried out. The two designs presented in this paper are suitable for real-time applications of multi-channel audio digital signal processing

MemBIST applet for learning principles of memory testing and generating memory BIST

The paper presents a software tool that demonstrates principles of RAM memory testing and of the memory BIST structure. The MemBIST software tool automatically generates built-in self-test blocks for a given memory matrix as a VHDL model of the whole system. As a complement to the BIST structure generator, a module for visualisation of selected RAM memory fault models, March C-test algorithm as well as a memory self-testing architecture principle is a part of the tool. The developed system was implemented as a Java applet what means its good compatibility regarding different hardware and operating system platforms, its safety and accessibility while it is placed on Internet. The presented MemBIST applet is useful as an educational tool and a training tool in built-in self-testing for RAM memories.

Various MDCT implementations in 0.35μ CMOS

MDCT is the most computationally intensive operation in most audio compression standards. The paper presents ASIC implementations of Ave 12/36-point MDCT architectures. All IP cores are capable of computing forward and backward MDCT and this makes them universal in multimedia SoCs for accelerating the MP3 compression/decompression. The main difference between the presented architectures is in their level of parallelization - from fully parallel to sequential architecture. The power consumption issues were observed with respect to different parallelization levels.

A tool for teaching memory testing based on BIST

The paper presents a tool that explains and demonstrates the essentials of RAM testing and memory built-in self-test. It also generates the BIST structure for the given memory matrix together with a march test which is provided by the march test generator according to the defined list of faults. The developed system was implemented as a Java applet what means its good compatibility regarding different hardware and operating system platforms, its safety and accessibility while it is placed on Internet. The presented tool has been utilised as the educational instrument in laboratory works