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Dive into the research topics where Marcel Lugthart is active.

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Featured researches published by Marcel Lugthart.


IEEE Journal of Solid-state Circuits | 2004

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS

Jan Mulder; Christopher M. Ward; Chi-Hung Lin; D. Kruse; Jan R. Westra; Marcel Lugthart; Erol Arslan; R.J. van de Plassche; Klaas Bult; F.M.L. van der Goes

This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-/spl mu/m CMOS ADC occupies 0.09 mm/sup 2/ and consumes 21 mW.


custom integrated circuits conference | 2011

A 19 mW/lane Serdes transceiver for SFI-5.1 application

Siavash Fallahi; Delong Cui; Deyi Pi; Rose Zhu; Greg Unruh; Marcel Lugthart; Afshin Momtaz

A low-power, small-area transceiver PHY that supports SFI-5.1 is fabricated in standard 40 nm CMOS, supporting rates up to 50 Gb/s. The combined active core area of the receiver (RX) and transmitter (TX) occupies only 0.08 mm2 per lane. The RX can handle 0.65 UI (RJ + DJ) plus 0.49 UI additional sinusoidal input jitter, and the TX has only 5.4 ps of ISI. Sixteen lanes plus deskew and clock source channels consume 19 mW of power at 3.125 Gb/s per lane.


international solid-state circuits conference | 2004

A 21mW 8b 125MS/s ADC occupying 0.09mm/sup 2/ in 0.13/spl mu/m CMOS

Jan Mulder; Christopher M. Ward; Chi-Hung Lin; D. Kruse; Jan R. Westra; Marcel Lugthart; Erol Arslan; R.J. van de Plassche; Klaas Bult; F.M.L. van der Goes

An 8b subranging ADC uses interpolation, averaging, offset compensation and pipelining techniques to accomplish 7.6b ENOB at 125MS/s. The 0.13/spl mu/m CMOS ADC occupies 0.09mm/sup 2/ and consumes 21 mW.


Archive | 2003

Single-ended-to-differential converter with common-mode voltage control

Jan Mulder; Marcel Lugthart; Chi-Hung Lin


Archive | 2003

SUBRANGING ANALOG TO DIGITAL CONVERTER WITH MULTI-PHASE CLOCK TIMING

Franciscus Maria Leonardus van der Goes; Jan Mulder; Christopher M. Ward; Jan R. Westra; Rudy van de Plassche; Marcel Lugthart


symposium on vlsi circuits | 2013

An 8.5 mW, 0.07 mm 2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter

Bo Shen; Greg Unruh; Marcel Lugthart; Chang-Hyeon Lee; Mark Chambers


international solid-state circuits conference | 2004

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS

Jan Mulder; Christopher M. Ward; Chi-Hung Lin; D. Kruse; Jan R. Westra; Marcel Lugthart; Erol Arslan; Rudy van de Plassche; Klaas Bult; Frank M. L. van der Goes


Archive | 2011

Switchable passive termination circuits

Joseph Aziz; Andrew Chen; Derek Tam; Ark-Chew Wong; Agnes Woo; Marcel Lugthart


Archive | 2009

Active termination and switchable passive termination circuits

Joseph Aziz; Andrew Chen; Derek Tam; Ark-Chew Wong; Agnes Woo; Marcel Lugthart


Archive | 2007

FAST AND POWER-EFFICIENT CMOS SUBRANGING ADCs

F.M.L. van der Goes; Jan Mulder; Christopher M. Ward; Chi-Hung Lin; D. Kruse; Jan R. Westra; Marcel Lugthart; Erol Arslan; Ovidiu Bajdechi; R.J. van de Plassche; Klaas Bult

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