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Dive into the research topics where Marcella Carissimi is active.

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Featured researches published by Marcella Carissimi.


european solid state circuits conference | 2017

A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications

Marco Pasotti; Marcella Carissimi; Chantal Auricchio; Donatella Brambilla; Emanuela Calvetti; Laura Capecchi; Luigi Croce; Daniele Gallinari; Cristina Mazzaglia; Vikas Rana; Riccardo Zurla; Alessandro Cabrini; Guido Torelli

The demand for more and more efficient management of power systems is causing BCD technologies to move forward in the integration of additional digital functions, and the use of microcontrollers in products has become a common practice. In this perspective, the introduction of an embedded nonvolatile memory (eNVM) to store the microcontroller code has become important to enable software customization. In this paper, a 32 KB embedded Phase Change Memory (ePCM) designed and manufactured in 0.11 μm Smart Power BCD technology with a specifically optimized Ge-rich Ge-Sb-Te alloy (supply voltage = 1.8 V) is presented. The ePCM features 18 ns random access time and robustness against resistance drift thanks to the used differential sensing scheme and 20 ßs word modify time with 32-cell programming parallelism thanks to enhanced programming circuits. The 32 KB eNVM size is 0.7 mm2.


Microelectronics Journal | 2018

Row decoder for embedded Phase Change Memory using low voltage transistors

Vikas Rana; Marco Pasotti; Marcella Carissimi

Abstract In this paper, a row decoder architecture is discussed, that is designed using low voltage transistors, targeting fast word-line charging. Total Read timings in any memory can be divided into two parts: Word-line (WL) capacitive load charging time and Sense amplifier reaction time. Word-Line charging time is decided by WL-driver, Row-decoder and pre-decoder stages, architecture and type of transistor used in circuits. Here, a Row-decoder architecture (specifically used for Phase Change Memories) is presented that can help in achieving fast WL charging during Read operation and during Modify operation, it can bias WL at high voltage without compromising the reliability. In this architecture, Low voltage transistors are used with separated low voltage and high voltage paths for Memory Read and Modify operations. All devices are operated in their safe operating area (SOA) ensuring reliability of circuit.


Archive | 2010

FTP memory device with programming and erasing based on Fowler-Nordheim effect

Marco Pasotti; Marcella Carissimi; Davide Lena


Archive | 2013

IDENTIFICATION OF A CONDITION OF A SECTOR OF MEMORY CELLS IN A NON-VOLATILE MEMORY

Marcella Carissimi; Marco Pasotti; Fabio De Santis


Archive | 2015

Error correction in differential memory devices with reading in single-ended mode in addition to reading in differential mode

Marcella Carissimi; Marco Pasotti


Archive | 2014

System and Method for Phase Change Memory

BharathManoj Manda; Abhishek Lal; Marco Pasotti; Marcella Carissimi


Archive | 2014

System and method for phase change memory with erase flag cells

BharathManoj Manda; Abhishek Lal; Marco Pasotti; Marcella Carissimi


IEEE Journal of Solid-state Circuits | 2018

A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications

Marco Pasotti; Riccardo Zurla; Marcella Carissimi; Chantal Auricchio; Donatella Brambilla; Emanuela Calvetti; Laura Capecchi; Luigi Croce; Daniele Gallinari; Cristina Mazzaglia; Vikas Rana; Alessandro Cabrini; Guido Torelli


Archive | 2017

SENSE AMPLIFIER FOR NON-VOLATILE MEMORY DEVICES AND RELATED METHODS

Marco Pasotti; Marcella Carissimi; Rajat Kulshrestha; Chantal Auricchio


Archive | 2017

Memory device including decoder for a program pulse and related methods

Marco Pasotti; Marcella Carissimi; Vikas Rana

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