Marcella Carissimi
STMicroelectronics
Network
Latest external collaboration on country level. Dive into details by clicking on the dots.
Publication
Featured researches published by Marcella Carissimi.
european solid state circuits conference | 2017
Marco Pasotti; Marcella Carissimi; Chantal Auricchio; Donatella Brambilla; Emanuela Calvetti; Laura Capecchi; Luigi Croce; Daniele Gallinari; Cristina Mazzaglia; Vikas Rana; Riccardo Zurla; Alessandro Cabrini; Guido Torelli
The demand for more and more efficient management of power systems is causing BCD technologies to move forward in the integration of additional digital functions, and the use of microcontrollers in products has become a common practice. In this perspective, the introduction of an embedded nonvolatile memory (eNVM) to store the microcontroller code has become important to enable software customization. In this paper, a 32 KB embedded Phase Change Memory (ePCM) designed and manufactured in 0.11 μm Smart Power BCD technology with a specifically optimized Ge-rich Ge-Sb-Te alloy (supply voltage = 1.8 V) is presented. The ePCM features 18 ns random access time and robustness against resistance drift thanks to the used differential sensing scheme and 20 ßs word modify time with 32-cell programming parallelism thanks to enhanced programming circuits. The 32 KB eNVM size is 0.7 mm2.
Microelectronics Journal | 2018
Vikas Rana; Marco Pasotti; Marcella Carissimi
Abstract In this paper, a row decoder architecture is discussed, that is designed using low voltage transistors, targeting fast word-line charging. Total Read timings in any memory can be divided into two parts: Word-line (WL) capacitive load charging time and Sense amplifier reaction time. Word-Line charging time is decided by WL-driver, Row-decoder and pre-decoder stages, architecture and type of transistor used in circuits. Here, a Row-decoder architecture (specifically used for Phase Change Memories) is presented that can help in achieving fast WL charging during Read operation and during Modify operation, it can bias WL at high voltage without compromising the reliability. In this architecture, Low voltage transistors are used with separated low voltage and high voltage paths for Memory Read and Modify operations. All devices are operated in their safe operating area (SOA) ensuring reliability of circuit.
Archive | 2010
Marco Pasotti; Marcella Carissimi; Davide Lena
Archive | 2013
Marcella Carissimi; Marco Pasotti; Fabio De Santis
Archive | 2015
Marcella Carissimi; Marco Pasotti
Archive | 2014
BharathManoj Manda; Abhishek Lal; Marco Pasotti; Marcella Carissimi
Archive | 2014
BharathManoj Manda; Abhishek Lal; Marco Pasotti; Marcella Carissimi
IEEE Journal of Solid-state Circuits | 2018
Marco Pasotti; Riccardo Zurla; Marcella Carissimi; Chantal Auricchio; Donatella Brambilla; Emanuela Calvetti; Laura Capecchi; Luigi Croce; Daniele Gallinari; Cristina Mazzaglia; Vikas Rana; Alessandro Cabrini; Guido Torelli
Archive | 2017
Marco Pasotti; Marcella Carissimi; Rajat Kulshrestha; Chantal Auricchio
Archive | 2017
Marco Pasotti; Marcella Carissimi; Vikas Rana