Vikas Rana

A 32KB 18ns random access time embedded PCM with enhanced program throughput for automotive and smart power applications

The demand for more and more efficient management of power systems is causing BCD technologies to move forward in the integration of additional digital functions, and the use of microcontrollers in products has become a common practice. In this perspective, the introduction of an embedded nonvolatile memory (eNVM) to store the microcontroller code has become important to enable software customization. In this paper, a 32 KB embedded Phase Change Memory (ePCM) designed and manufactured in 0.11 μm Smart Power BCD technology with a specifically optimized Ge-rich Ge-Sb-Te alloy (supply voltage = 1.8 V) is presented. The ePCM features 18 ns random access time and robustness against resistance drift thanks to the used differential sensing scheme and 20 ßs word modify time with 32-cell programming parallelism thanks to enhanced programming circuits. The 32 KB eNVM size is 0.7 mm2.

Row decoder for embedded Phase Change Memory using low voltage transistors

Abstract In this paper, a row decoder architecture is discussed, that is designed using low voltage transistors, targeting fast word-line charging. Total Read timings in any memory can be divided into two parts: Word-line (WL) capacitive load charging time and Sense amplifier reaction time. Word-Line charging time is decided by WL-driver, Row-decoder and pre-decoder stages, architecture and type of transistor used in circuits. Here, a Row-decoder architecture (specifically used for Phase Change Memories) is presented that can help in achieving fast WL charging during Read operation and during Modify operation, it can bias WL at high voltage without compromising the reliability. In this architecture, Low voltage transistors are used with separated low voltage and high voltage paths for Memory Read and Modify operations. All devices are operated in their safe operating area (SOA) ensuring reliability of circuit.

A 10 MHz, 42 ppm/\( ^{ \circ } {\text{C}} \), 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM

In this paper, a PVT compensated, 10 MHz oscillator in 0.11 µm BCD9S (Bipolar CMOS DMOS) technology for embedded phase change memories (PCM) is reported. The proposed oscillator produces a frequency deviation of ±0.4% for typical corner, ±2% for slow corner and ±1.5% for fast corner around 10 MHz across −40 °C to 150 °C at a regulated supply of 1.8 V. It is a significant advancement in the existing state-of-the-art for frequency references.

A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator

A 10 MHz, 84 μW PVT compensated ring oscillator is presented in 0.11 μm BCD9S (Bipolar CMOS DMOS) technology. The proposed ring oscillator is inherently temperature compensated and produces a frequency deviation of ±0.7% in typical corner, ±2.25% in slow corner and ±0.75% in fast corner around 10 MHz across −40 °C to 150 °C at a regulated supply of 1.8 V. The proposed oscillator exhibits less sensitivity to PVT variations and requires less area when compared to the state-of-the-art oscillators.

-1.1V to +1.1V 3:1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI

Temperature dependent body bias modulation of array reduces SRAM VMIN thereby reducing overall dynamic power. Fully Depleted Silicon On Insulator (FDSOI) technology offers single P-well SRAM bit cell that can be biased to positive voltages upto +1.1V to boost write-ability at cold temperatures and upto-1.1V to boost stability at hot temperatures. In this paper, we present the architecture and design of a 3:1 body bias power switch that can transmit positive, negative and zero voltage depending on the input from an on-chip temperature sensor. All the devices operate within their safe operating area (SOA) ensuring reliability. The implementation was done using extended gate devices supporting 1.8V operation in 28nm planar Ultra-Thin Box and Body, FDSOI CMOS (UTBB FDSOI) technology.