Marcellinus J. M. Pelgrom

A 3/5 V compatible I/O buffer

The design of a digital input/output buffer is described for operation in 3.3-V ICs with 5-V input signals. The design has been processed in 0.8- and 0.6-/spl mu/m CMOS processes. A comparison of results is presented. >

A 25-Ms/s 8-bit CMOS A/D converter for embedded application

The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm/sup 2/ in a 1 /spl mu/m CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip. >

A CCD Delay Line for Video Applications

A surface channel Charge-Coupled Device is used for delaying one television line. The chip uses 4 analog-multiplexed lines and has on-chip circuits for adapting to clock frequencies that can occur in various types of video equipment. The 4.8mm2 chip requires only 40 mW from a 5 volt supply.