Marcin Jastrzab

Design and test of a high-speed flash ADC mezzanine card for high-resolution and timing performance in nuclear structure experiments

This work describes new electronics for the EXOGAM2 (HP-Ge detector array) and NEDA (BC501A-based neutron detector array). A new digitizing card with high resolution has been designed for gamma-ray and neutron spectroscopy experiments. The higher bandwidth requirement of the NEDA signals, together with the necessity for accuracy, require a high sampling rate in order to preserve the shape for real-time Pulse Shape Analysis (PSA). The PSA is of paramount importance for the NEDA to discriminate between neutrons and -ray signals. Both high resolution and high speed parameters are often difficult to achieve in a single electronic unit. These constraints, together with the need to build new digitizing electronics to improve performance and flexibility of signal analysis in nuclear physics experiments, led to the development a new FADC mezzanine card. In this work, the design and development are described, including the characterization procedure and the preliminary measurement results.

Fully depleted monolithic active pixel sensor in SOI technology

An active pixel detector, which exploits wafer-bonded silicon on insulator (SOI) substrates for integration of the readout electronics with the pixel detector, is presented. The main concepts of the proposed monolithic sensor and the preliminary tests results with ionising radiation sources are addressed. Silicon on insulator is an alternative solution for a monolithic active pixel detector, which allows integrating a fully depleted sensor and front-end electronics active layers into one silicon wafer. The main idea of the sensor relies on the use of both monolithic silicon layers (device and support layers) of the SOI substrate for fabrication of pixel detector diodes and readout electronics. Such detectors can find wide range of applications, not only in particle physics but also in medicine, space science and many other disciplines. The sensor structure and the readout configuration have been developed and the measurements of a dedicated test structure have validated the new technology of the SOI detector. Small SOI sensor matrices with 8 by 8 channels have been recently produced and tested.

Design and Performance of a DNW CMOS Active Pixel Sensor for the ILC Vertex Detector

The SDR0 (Sparsified Digital Readout) prototype is a proof-of-principle design which is aimed at studying the feasibility of pixel level sparsified digital readout in CMOS MAPS matching the requirements for the Vertex Detector at the International Linear Collider. The deep n-well (DNW) available in deep sub-micron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. The chip has been designed in a 130 nm triple-well CMOS process and fabricated by STMicroelectronics. This first prototype includes a 16 times 16 DNW-MAPS matrix with sparsified readout architecture, an 8 times 8 matrix with digital output and selectable access to the analog output in each cell, and a 3 × 3 matrix with all the analog outputs available at the same time. The analog front-end has been characterized and the digital readout circuits have been successfully tested at frequencies up to 50 MHz. The circuit design and the performance of SDR0 are discussed in this paper.

Performance of a DNW CMOS active pixel sensor designed for the ILC Vertex Detector

The SDR0 (Sparsified Digital Readout) prototype is a proof-of-principle design which is aimed at studying the feasibility of pixel level sparsified digital readout in CMOS MAPS matching the requirements for the Vertex Detector at the International Linear Collider. The deep n-well (DNW) available in deep sub-micron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. The chip has been designed and fabricated in a 130nm triple-well CMOS process by STMicroelectronics. This first prototype includes a 16×16 DNW-MAPS matrix with sparsified readout architecture, an 8×8 matrix with digital output and selectable access to the analog output in each cell, and a 3×3 matrix with all the analog outputs available at the same time. The analog front-end has been characterized and the digital readout circuits have been successfully tested at frequencies up to 50MHz. The circuit design and the performance of SDR0 are discussed in this paper.

TEST OF REAL-TIME IDENTIFICATION OF SPARSE DATA PATTERNS IN SILICON PIXEL DETECTORS

MARCIN JASTRZAB, ANTONIO BULGHERONI, MASSIMO CACCIA, CHIARA CAPPELLINI, GRZEGORZ CHWIERUT, WOJCIECH KUCEWICZ, FABIO RISIGO Electronics Department, AGH-University of Science and Technology, Al. Mickiewicza 30, Krakow 30-059, Poland Dipartimento di Scienze CC.FF.MM., Universita dell’Insubria, via Valleggio 11, 22100 Como, Italy Dipartimento di Fisica, Universita di Roma 3 e INFN Sezione di Roma 3, via della Vasca Navale 84, 00146 Roma, Italy