S. Kuta

Silicon ultra fast cameras for electron and γ sources in medical applications

Abstract SUCIMA (Silicon Ultra fast Cameras for electron and γ sources In Medical Applications) is a project approved by the European Commission with the primary goal of developing a real time dosimeter based on direct detection in a Silicon substrate. The main applications, the detector characteristics and technologies and the data acquisition system are described.

Hybrid active pixel sensors and SOI inspired option

Abstract Two novel pixel sensor concepts for future linear collider applications are presented in this paper: a hybrid pixel sensor characterized by a layout improving the single point resolution and a monolithic detector inspired by silicon on insulator (SOI) technology. The results of charge collection studies for the first prototypes of hybrid pixel sensors with interleaved pixels are reported and the new detector test structures are introduced. The technology and the readout architecture design for SOI sensors are also discussed.

Four-quadrant Analog Multiplier Based On CMOS Inverters

The paper describes a new four-quadrant analog multiplier CMOS implementation based on CMOS inverters and exploiting quadrature technique. An outstanding feature of this circuit solution is suitability for low voltage operation reaching the extreme for the analog part, since there are only two transistors is tacked in between supply rails. The circuit in question is symmetric driven and fully balanced. The operation principle is described as well as simulation results are presented

Current Mode Circuit Implementations of PWL Functions

Current-mode techniques have been used to realize improved basic building blocks of elementary piecewise linear (PWL) functions. These alternative circuit implementations, used for synthesis of precision PWL transfer characteristics, are described and compared in performance. In this paper, two optional topologies of the PWL function building blocks are proposed, based on the regulated cascode current mirror, current sources, Schottky “prebiased” diodes, and improved CMOS class AB “prebiased diodes.” The comparison of DC and high frequency performances is based on HSPICE simulation results and shows very good DC accuracy and transient time response of the proposed building blocks.

Current controlled delay line elements' improvement study

The chain of delay elements creating delay lines are the basic building blocks of delay locked loops (DLLs) applied in clock distribution network in many VLSI circuits and systems. In the paper Current Controlled delay line (CCDL) elements with Duty Cycle Correction (DCC) has been described and investigated. The architecture of these elements is based on Switched-Current Mirror Inverter (SCMI) and CMOS standard or Schmitt type inverters. The primary characteristics of the described CCDL element have been compared with characteristics of two most popular ones: current starved, and shunt capacitor delay elements. The simulation results with real foundry parameters models in 180 nm, 1.8 V CMOS technology from UMC are also included. Simulations have been done using BSIM3V3 device models for Spectre from Cadence Design Systems.

Monolithic active pixel sensor realized in SOI technology—concept and verification

The paper presents the concept and the verification of a novel silicon monolithic active pixel detector realized in the SOI technology. The reliability and the basic electrical characteristics of the sensor are studied and the sensor sensitivity to the ionising radiation is investigated in details.

Fully depleted monolithic active pixel sensor in SOI technology

An active pixel detector, which exploits wafer-bonded silicon on insulator (SOI) substrates for integration of the readout electronics with the pixel detector, is presented. The main concepts of the proposed monolithic sensor and the preliminary tests results with ionising radiation sources are addressed. Silicon on insulator is an alternative solution for a monolithic active pixel detector, which allows integrating a fully depleted sensor and front-end electronics active layers into one silicon wafer. The main idea of the sensor relies on the use of both monolithic silicon layers (device and support layers) of the SOI substrate for fabrication of pixel detector diodes and readout electronics. Such detectors can find wide range of applications, not only in particle physics but also in medicine, space science and many other disciplines. The sensor structure and the readout configuration have been developed and the measurements of a dedicated test structure have validated the new technology of the SOI detector. Small SOI sensor matrices with 8 by 8 channels have been recently produced and tested.

Double edge class BD hybrid DPWM implementation using linearized LBDD algorithm

In the paper we propose a novel architecture and implementation of 10-bit Digital Pulse Width Modulator (DPWM) circuit based on previously known building blocks. Linearized Class-BD Double-sided (LBDD) algorithm has been used to calculate the DPWM signals of the 10-bit resolution hybrid DPWM for a Class-D digital audio amplifier. Noise-shaping process is used to support high fidelity with feasible values of time resolution. The proposed DPWM circuit is composed of two 6-bit counters and one Analog Delay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fine programmable delay elements has been presented elsewhere [12]. The proposed 10-bit DPWM circuit, at switching frequency of 352.8 kHz, clock frequency of 45 MHz allows to attain SNR of 120 dB and THD of the output signal less than 0,1% within the audio baseband and modulation index of 0.98. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) for one CMOS process are presented.

Hybrid DPWM implementation using coarse and fine programmable ADLL

abstract In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse WidthModulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybridDPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity withpractical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and AnalogDelay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fineprogrammable delay element is used to adjust the delay time of delay line and lock it to required time.The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based onshunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at aswitching frequency of 352.8 kHz and clock generator frequency of 90.3 MHz allows us to attain SNR of120 dB and THD of the output signal less than 0.1% within the audio baseband and modulation indexM¼0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) forreal CMOS process are presented.& 2014 Elsevier Ltd. All rights reserved.

Low voltage charge-pump-based VCO circuits using CMOS inverters as building blocks

In the paper a circuit implementation of CMOS voltage controlled oscillator is presented. The most interesting feature of the presented proposal is extreme low voltage suitability, because CMOS inverters are used as main building blocks. The simulation results with real foundry parameters are also included.