Marco Antonio Gurrola-Navarro

A digitally programmable active resistor in CMOS technology

A technique for the implementation of a programmable grounded and floating resistors is presented. The grounded version of the resistor has been implemented in a standard CMOS technology, where a set of digital inputs allows the programming of the circuit. The performance of the circuit is shown by means of DC, AC, Transient and Monte Carlo simulations. Measurements on a 0.35 μm CMOS physical implementation are presented. Additionally, an application of the proposed circuit in programmable filters is described.

Experimental analysis of a transconductor-amplifier based on a mi-fgmos transistor

This is an analysis of a common source CMOS transconductor based on a Multiple-input Floating Gate MOS transistor with feedback configuration. This analysis allows to visualize the specific way to find the operating point of the amplifier, when it is used as a transconductor. In this work, both theoretical and experimental results are presented. Here, the problem of improving the theoretical data is discussed. Transconductor cells were manufactured using the TSMC technology for 0.35μm. The data obtained here facilitate the design of complex transconductor based on the use of multiple input floating gate MOS transistor in analog integrated circuits.

Using the EKV model to describe the DC operation in weak inversion of the multiple-input FGMOS transistor

The Floating Gate MOS Transistor with Multiple Inputs is a device that offers some advantages with regard to the conventional MOS transistor. However, even today, there is a lack of formal and detailed analysis about the analog model in the literature. An accurate model of this device is very important for designing high performance analog cells. In this document a strategy for modeling the floating gate transistor operating in the weak inversion region based in the adaptation of the EKV model is proposed. The basis for developing a complete theory which allows the modeling of this device model is introduced. This type of modeling can be very useful for high performance analog integrated circuits designers where the transistor concerned here is strongly recommended. Further, this modeling process is also useful for the development of new computational tools for analog circuits simulation.

A technique to improve the transconductance in amplifiers

This paper presents a technique for improving the response of amplifier implemented with multiple inputs floating gate transistor for processing input signals of very small amplitude. With the technique presented here, it is possible to improve the transconductance of the amplifier, maintaining all the positive features of the device as variable threshold voltage and very-low voltages applications. This document shows the proposed technique and its implementation in SPICE using CMOS technological parameters for 0.35 μm process. Additionally, the results obtained using a common source amplifier to validate the feasibility of the proposed technique are included.

Extracting the floating gate voltage on the multiple-input FGMOS transistor

The extraction of the floating gate voltage on the Multiple-Input Floating-Gate Transistor is discussed in order to understand their behavior in a better way. The lack of linearity at very low voltage is discussed. The presence of a residual charge on the floating gate is experimentally shown despite the use of metal contact to discharge it. This analysis is useful to enhance the mathematical model and consequently to have better results in the simulation process especially when this device is used as an entirely analog processing element. Methods to extract and plot the floating gate voltage are addressed. A comparison between analytical and experimental results is shown.

A highly linear differential amplifier with tunable gain

This article presents a strategy for implementing a differential amplifier that allows a high degree of linearity in the output currents with tunable gain. For this purpose, multiple-input floating-gate transistors are used, along with a technique for increasing the transconductance by means of a sum of currents. Simulation results are presented for a 0.35-μm technology. The differential amplifier offers a maximum gain of 62V/V and a bandwidth of 100KHz with a 5pF capacitive load. The total harmonic distortion obtained is 0.273%.

Delay in QRS complex detection using the wavelet transform for real-time applications

Pattern recognition is a widespread application of the Wavelet Transform (WT). Sometimes, in real-time implementations a delay as low as possible is desired in the pattern detection process. This is especially important in applications such as breath or electrocardiogram (ECG) monitoring for life-support. Nevertheless, any real-time WT system which is actually implemented can present different sources of delay due to the algorithm implementations, electrical signals propagation or even due to fundamental mathematical limitations. In this work is shown that the impulse response of a continuous band-pass filter (wavelet function) has some mathematical characteristics that allow the reduction of delay in pattern detection systems for low frequency signals. The performance of the biquadratic response is compared with the Gaussian first derivative and Mexican Hat wavelets. For the experimental part of this work, we have used an FPGA with softcore Nios II performing a WT system for QRS complex detection in ECG signals using eight scales. The experimental results show that the biquadratic wavelet allows a zero or even negative delay, which never is reached when any of the classical wavelets is used. The detection errors (as low as 0.25%) are similar for the Gaussian and biquadratic wavelets.

VLSI architecture of a Kalman filter optimized for real-time applications

This paper presents a parametrized VLSI architecture for an nstate Kalman filter implementation intended for real-time applications that typically require a sensing rate not far from 300 samples per second. The architecture has been optimized in silicon area and power consumption. This approach has been proved with a fabricated chip using a 0.5 μm CMOS technology. The fabricated integrated circuit executes a two-state Kalman filter employing 70K transistors. For a performance of 50 filter iterations/ second, the chip requires a clock frequency of 200KHz where a negligible power consumption of 1.1mW is observed. This performance can be increased up to 176,991 iterations/second at a clock frequency of 20MHz.

Design and validation of a mixed-signal correlator using a multiple-input floating gate transistor

The design and validation of an architecture of a CMOS mixed-signal correlator in VLSI technology based on the Multiple-Input Floating Gate MOS Transistor is introduced. The key element of this architecture is a single transistor with 513 inputs. The system includes one pair of configurable shift registers, a comparator stage with hysteresis and an output stage. The correlator is designed for processing sequences of 256 bits and is validated for a technology process of 0.35μm. The novel proposed architecture is described here and its operation is validated using simulation tools. We discuss ways to resolve the problems of simulation generated by the use of the 513-input floating gate device. The architecture is proposed to operate at low voltage.

Automatic On-Die Impedance Matching in Current Mode Off-Chip Signaling

A system for on-die automatic impedance matching in current mode off-chip signaling is described. In order to perform the automatic matching operation, an algorithm that integrates the sign of the impedance matching error and the sign of the coupling branch current is implemented. An advantage of the proposed system is that it works without interfering with the driver operation. The transistor level circuit implementation of the system is described and computational simulations with post layout extractions are presented. Also experimental results are shown in order to prove the performance of the system.