Miguel Angel Garcia-Andrade

Efficient Dithering in MASH Sigma-Delta Modulators for Fractional Frequency Synthesizers

The digital multistage-noise-shaping (MASH) ΣΔ modulators used in fractional frequency synthesizers are prone to spur tone generation in their output spectrum. In this paper, the state of the art on spur-tone-magnitude reduction is used to demonstrate that an M -bit MASH architecture dithered by a simple M-bit linear feedback shift register (LFSR) can be as effective as more sophisticated topologies if the dither signal is properly added. A comparison between the existent digital ΣΔ modulators used in fractional synthesizers is presented to demonstrate that the MASH architecture has the best tradeoff between complexity and quantization noise shaping, but they present spur tones. The objective of this paper was to significantly decrease the area of the circuit used to reduce the spur tone magnitude for these MASH topologies. The analysis is validated with a theoretical study of the paths where the dither signal can be added. Experimental results of a digital M -bit MASH 1-1-1 ΣΔ modulator with the proposed way to add the LFSR dither are presented to make a hardware comparison.

Third-order ΣΔ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW

This low-power sigma-delta modulator targets the DVB-H requirements and achieves about 10 bit with 6-MHz signal band and a FoM of 0.59 pJ/conversion. The used scheme is a multi-bit third order modulator that, with suitable topological modification, enables using two op-amps and enjoying a swing reduction at the quantizer input. The area of the circuit, fabricated with a 0.18-mum analog CMOS technology, is 0.32 mum2. The nominal supply voltage is 1.8 V and the clock frequency is 96 MHz (OSR = 8). Experimental measurements confirm the behavioral study made accounting for the op-amps limitations.

Automatic impedance control for chip-to-chip interconnections

The automatic control of the matching impedance in chip-to-chip interconnections is described. The proposed method is based on an optimization algorithm that uses the sign of error and the sign of the coupling branch current. A possible implementation of the system is described and computer simulations at the behavioral level are presented.

Accurate models for Frequency Synthesizers

An accurate Noise description in behavioral models for Fractional-N Frequency Synthesizers is presented. It is demonstrated that a noise-addition-like synthesizerpsilas model yields a better Phase-Noise prediction than a time-domain jitter model. This allows a more direct analysis of the noise contribution of every circuit in the Frequency Synthesizers and avoids simulation inaccuracies when very low Phase-Noise designs are held.

Optimal dithered digital sigma-delta modulators for fractional-N frequency synthesizers

By using a structured dither addition it is demonstrated how a very simple 8-bit linear feedback shift register (LFSR) can be used to randomize a digital MASH 1-1-1 SigmaDelta modulator used for fractional-N frequency synthesizers. With this optimization, spur tones for high frequency offset from the carrier are avoided without significant area and power budget increase.

A digitally programmable active resistor in CMOS technology

A technique for the implementation of a programmable grounded and floating resistors is presented. The grounded version of the resistor has been implemented in a standard CMOS technology, where a set of digital inputs allows the programming of the circuit. The performance of the circuit is shown by means of DC, AC, Transient and Monte Carlo simulations. Measurements on a 0.35 μm CMOS physical implementation are presented. Additionally, an application of the proposed circuit in programmable filters is described.

A self tuning system for on-die terminators in current mode off-chip signaling

A system for self tuning of on-die terminators in current mode off-chip signaling is presented. The proposed method is based on an algorithm that uses the sign of the impedance matching error and the sign of the coupling branch current to perform the self tuning operation. The circuit implementation of the system is described and computer simulations at the transistor level are presented for process, temperature and load impedance variations.

Automatic On-Die Impedance Matching in Current Mode Off-Chip Signaling

A system for on-die automatic impedance matching in current mode off-chip signaling is described. In order to perform the automatic matching operation, an algorithm that integrates the sign of the impedance matching error and the sign of the coupling branch current is implemented. An advantage of the proposed system is that it works without interfering with the driver operation. The transistor level circuit implementation of the system is described and computational simulations with post layout extractions are presented. Also experimental results are shown in order to prove the performance of the system.

Limitations of the Phase-to-Frequency-Detector in Fractional Frequency Synthesizers

In this paper a closed form expression for the Phase-to-Frequency-Detector (PFD) output error, in Fractional Frequency Synthesizers, is obtained. It is demonstrated that the limit frequency of operation for the PFD not only depends on the reset delay signal but also in the setup time of the PFD. With this equations a suitable delay in the reset signal can be selected.