Marco Crepaldi

An Ultra-Low-Power interference-robust IR-UWB transceiver chipset using self-synchronizing OOK modulation

Impulse Radio-UWB (IR-UWB) is actively being researched as a low cost wireless technology for Ultra Low Power (ULP), low data-rate, short-range wireless links in tagging [1], sensing and medical applications. In current solutions efficient timing acquisition as well as Narrow-Band Interference (NBI) rejection requires complex or large analog and digital circuits [2–4]. In this work, we introduce an IR-UWB architecture with very high NBI rejection and present a low complexity and low power timing synchronization and demodulation technique while achieving excellent link performance.

An Ultra-Wideband Impulse-Radio Transceiver Chipset Using Synchronized-OOK Modulation

This work presents a low-complexity IR-UWB chipset which achieves synchronization and demodulation at the receiver relying only on a ring oscillator clock. The modulation scheme used, synchronized-OOK (S-OOK), permits low power timing acquisition and data reception with a static CMOS digital synchronizer and demodulator counting 61 logic elements. The receiver consists of a modified energy detector (ED) that allows to asynchronously receive UWB pulses in presence of narrowband interference (NBI) with power levels up to -5 and -16 dBm for 5.4 and 2.4 GHz continuous wave interfering signals respectively. The sensitivity is -60/ -66 dBm with an overall energy dissipation of 2.9/3.9 nJ/bit for a 1 Mbps S-OOK PRBS data stream and a 100% power duty cycle. The complete demodulation and synchronization digital back-end consumes only 0.2 mW (including on-chip output buffers) during normal operation. The IR-UWB transmitter is based on a gated LC oscillator and achieves pulse durations of ~2 ns for bandwidths of 500 MHz. It consumes 249 pJ/bit energy per bit at 1 Mbps OOK.

A Very Low-Complexity 0.3–4.4 GHz 0.004 mm

This paper presents a very low-complexity all-digital IR-UWB transmitter that can generate pulses in the band 0-5 GHz, requiring a silicon area lower than a PAD for signal I/O. The transmitter, suited to non-standardized low data rate applications, is prototyped in a 130 nm RFCMOS technology and includes analog control signals for frequency and bandwidth tuning. Center frequency is linearly selected with voltage supply, 0.5 V for the range 0-960 MHz and 1.1 V supply for the higher 3.1-5 GHz range. The architecture is based on the same delay cell for both baseband and radio frequency signal generation and pulses fractional bandwidth remains constant when voltage supply and control voltages scale. At 420 MHz center frequency, the transmitter achieves 7 pJ/pulse, and for 4 GHz center frequency pulses, it achieves 32 pJ/pulse active energy consumption. The OOK/S-OOK transmitter occupies an area of 0.004 mm2. For ASK modulation, the system includes a separate on-chip capacitor bank connected to the output of the transmitter for an overall size of 0.024 mm2. For pulse rates below 100 kpps, the generated pulses meet the FCC indoor mask with an off-chip DC block capacitor. The paper also presents over-the-air measurements using a planar monopole antenna operating in the 1.5-3.7 GHz frequency range.

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We report design and measurements on a 0.13 μm CMOS Schmitt Trigger-based quasi-digital resistance-to-frequency converter prototype that can be effectively used as a read-out circuit for nanodevice-based sensors. The readout circuit comprises an operational amplifier and an inverting Schmitt Trigger, achieving an hysteresis scaled to 1 mV-order, hence, increasing frequency compared to a standard Schmitt Trigger RC oscillator. Experimental results obtained through an opto-isolated PCB set-up show maximum 0.8% RL measurement accuracy and a dynamic range between 50 kΩ and 3 GΩ . The flexible R-to-F converter occupies ~ 0.005 mm2 silicon area and has a simulated power consumption of 142 μW at 1.2 V supply.

All-Digital Ultra-Wide-Band Pulsed Transmitter for Energy Detection Receivers

Ultrawideband (UWB) communication based on the impulse radio paradigm is becoming increasingly popular. According to the IEEE 802.15 WPAN low rate alternative PHY Task Group 4a, UWB will play a major role in localization applications, due to the high time resolution of UWB signals which allow accurate indirect measurements of distance between transceivers. Key for the successful implementation of UWB transceivers is the level of integration that will be reached, for which a simulation environment that helps take appropriate design decisions is crucial. Owing to this motivation, in this paper we propose a multiresolution UWB simulation environment based on the VHDL-AMS hardware description language, along with a proper methodology which helps tackle the complexity of designing a mixed-signal UWB system-on-chip. We applied the methodology and used the simulation environment for the specification and design of an UWB transceiver based on the energy detection principle. As a by-product, simulation results show the effectiveness of UWB in the so-called ranging application, that is the accurate evaluation of the distance between a couple of transceivers using the two-way-ranging method.

A

Ultra wide band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VHDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VHDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations.

0.13~\mu{\rm m}

By using two separate components, mem-sensing devices can be fabricated combining the sensitivity of a transducer with non-volatile memory. Here, we discuss how a mem-sensor can be fabricated using a single material with built-in sensing andmemory capabilities, based on ZnO microwires (MWs) embedded in a photocurable resin and processed from liquid by vertically aligning the MWs across the polymeric matrix using dielectrophoresis. This results in an ultraviolet (UV) photodetector, a device that is widely applied in fields such as telecommunication, health, and defense, and has so far implemented using bulk inorganic semiconductors. However, inorganic detectors suffer from very high production costs, brittleness, huge equipment requirements, and low responsivity. Here, we propose for the first time aneasy processable, reproducible, and low-cost hybrid UV mem-sensor. Composites with aligned ZnO MWs produce giant photocurrentscompared to the same composites with randomly distributed MWs. In particular, we efficiently exploit a mem-response where the photocurrent carries memory of the last electronic state experienced by the device when under testing. Furthermore, we demonstrate the non-equivalence of different wave profiles used during thedielectrophoresis: a pulsed wave is able to induce order in both the axis and the orientation of the MWs, whereas a sine wave only affects the orientation.

CMOS Operational Schmitt Trigger R-to-F Converter for Nanogap-Based Nanosensors Read-Out

The brain signal anticipates the voluntary movement with patterns that can be detected even 500ms before the occurrence. This paper presents a digital signal processing unit which implements a real-time algorithm for falling risk prediction. The system architecture is designed to operate with digitized data samples from 8 EMG (limbs) and 8 EEG (motor-cortex) channels and, through their combining, provides 1 bit outputs for the early detection of unintentional movements. The digital architecture is validated on an FPGA to determine resources utilization, related timing constraints and performance figures of a dedicated real-time ASIC implementation for wearable applications. The system occupies 85.95% ALMs, 43283 ALUTs, 73.0% registers, 9.9% block memory of an Altera Cyclone V FPGA for a processing latency lower than 1ms. Outputs are available in 56ms, within the time limit of 300ms, enabling decision taking for active control. Comparisons between Matlab (used as golden reference) and measured FPGA outputs outline a very low residual numerical error of about 0.012% (worst case) despite the higher float precision of Matlab simulations and losses due to mandatory dataset conversion for validation.

A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver

This paper presents an ultra-low-power radio receiver implemented only with CMOS logic gates used as basic building blocks and proves its operation. The self-timed duty-cycled system is self-synchronized with the input radio signal, runs a noise-robust baseband detection and does not require any reference besides power supply. Based on S-OOK modulation, the 350-450 MHz digital radio RX occupies an area of 0.07 mm 2 in a 130 nm RFCMOS technology and achieves a 0.1% sensitivity of -63 dBm at 95 kbps, 380 MHz center frequency and 40 μW active power consumption at 1.1 V power supply. At 1.0 V it achieves -62 dBm sensitivity and 33 μW active power at ~ 0.1% error rate. The compact receiver, whose architecture is parametric and technology scalable, suits energy harvested and miniaturized biomedical applications. The paper also presents the potential advantages of asynchronous logic pulse radio and introduces an ad-hoc VHDL model demonstrating RTL-/gate-level accurate error-rate predictions capabilities based on digital simulation only, i.e., without requiring electrical-level co-simulation.

Energy detection UWB receiver design using a multi-resolution VHDL-AMS description

Smart Systems collate leading technologies and solutions for the design of new generation embedded and cyber-physical systems. They can be applied to a broad range of application domains, from everyday life to mission and safety critical tasks, and achieve a wide set of functionality using diverging architectures. Smart system design needs to be achieved in a real multi-domain environment, where analog, digital, mixed-signal, and now even MEMS sub-systems tightly interact. With a traditional approach, these different units are designed separately, and finally merged at the electronic system level. However, given the increasing integration and interactions among components of different nature, methodologies enabling effective system-level architectural exploration are becoming more and more significant. Starting from a detailed analysis and classification of state-of-the-art use scenarios, and based on a review of the existing approaches, we present a top-down constraint-driven methodology for the design of new generation smart systems. It enables partitioning and propagation of high-level application-driven requisites towards low-level units in the design flow. The methodology reviews fundamental and cross-sectional system-level design aspects applied to the definition of an example case, to identify sub-system requirements towards the specifications of the electrical features of each internal unit.