A. Gabrielli

A fast digital fuzzy processor

This digital fuzzy processor-designed and realized in 0.7-μm CMOS technology-demonstrates a processing rate from 80 to 320 ns. A parallel pipeline architecture supports fast selection of the active fuzzy rules. Specifically, we designed an Active-Rule-Selector for selecting a subset of the fuzzy rules, called active fuzzy rules, and divided the architecture into parallel and pipeline stages. Despite some initial difficulty, step by step our efforts yielded ever more feasible solutions. The foundry delivered the chip in 1997. So far, it works properly.

Measurement of the atmospheric muon flux with the NEMO Phase-1 detector

Abstract The NEMO Collaboration installed and operated an underwater detector including prototypes of the critical elements of a possible underwater km3 neutrino telescope: a four-floor tower (called Mini-Tower) and a Junction Box. The detector was developed to test some of the main systems of the km3 detector, including the data transmission, the power distribution, the timing calibration and the acoustic positioning systems as well as to verify the capabilities of a single tridimensional detection structure to reconstruct muon tracks. We present results of the analysis of the data collected with the NEMO Mini-Tower. The position of photomultiplier tubes (PMTs) is determined through the acoustic position system. Signals detected with PMTs are used to reconstruct the tracks of atmospheric muons. The angular distribution of atmospheric muons was measured and results compared to Monte Carlo simulations.

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

The Data Acquisition and Transport Design for NEMO Phase 1

The NEMO collaboration proposes to build an underwater neutrino telescope located South-East off the Sicily coast. This paper describes the concepts underlying the communication link design going over the whole data acquisition and transport from the front-end electronics to the module sending data on-shore through a fiber optic link which relies on Dense Wavelength Division Multiplexing. An on-shore board, plugged into a PC, extracts and distributes data both to first-level trigger and control systems. Underwater apparatus monitoring and controls are guaranteed by oceanographic instruments and dedicated sensors, whose data are packed and sent back to shore using the same optical link. The communication is fully bidirectional, allowing transmission of timing and control commands. The architecture described here provides a complete real-time data transport layer between the onshore laboratory and the underwater detector. During winter 2006 a first prototype of the apparatus has been deployed: calibration results from the currently working system are here reported.

Very fast rate 2-input fuzzy processor for high energy physics

The paper explains the design and the realization of a small size high-speed fuzzy processor. The processor goal is to give more flexibility to the front-end electronics for high-energy physics experiments. The chip can be applied as a general purpose data analyzer; particularly for analyzing and reducing on-line the data coming from detectors. The application of a fuzzy processor to this field allows rejecting redundant data in a very short time. The design of the fuzzy processor has been done using VHDL language; it is cell-based and has been implemented with Alcatel 0.35 µm CMOS VLSI technology. The chip architecture is pipelined with a clock frequency of 133 MHz; consequently the processing rate is 30 ns since only four active rules are processed. The chip size is 3 mm2 and the total power consumption is 200 mW with 3, 3 V of voltage supply.

Proposal of a data sparsification unit for a mixed-mode MAPS detector

The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.

Monolithic 180 nm CMOS Dosimeter for In Vivo Medical Applications

The design and development of a monolithic system-on-chip silicon device for real time measurement of radiation dose is described. The device is fabricated in a standard 180 nm CMOS technology. The proposed application is in the medical field of In Vivo Dosimetry, where the dose of radiation, delivered to patients during radiotherapy sessions, is monitored in real time by an in-body implanted device of 1 mm3 approximate size and the related information is transmitted wirelessly to an external receiver operating in the Medical Implant Communication Service (MICS) band. Along with standard electrical characterization, evaluation of device performance is carried out under radiation beam in a clinical environment. The design and initial test results of the first phase of the project, covering the radiation sensors, will be discussed. A description of the next project steps will also be given.

SCOPRISM: A new algorithm for automatic sleep scoring in mice

BACKGROUND Scoring of wake-sleep states by trained investigators is a time-consuming task in many sleep experiments. We aimed to validate SCOPRISM, a new open-source algorithm for sleep scoring based on automatic graphical clustering of epoch distribution. METHODS We recorded sleep and blood pressure signals of 36 orexin-deficient, 7 leptin knock-out, and 43 wild-type control mice in the PRISM laboratory. Additional groups of mice (n=14) and rats (n=6) recorded in independent labs were used to validate the algorithm across laboratories. RESULTS The overall accuracy, specificity and sensitivity values of SCOPRISM (97%, 95%, and 94%, respectively) on PRISM lab data were similar to those calculated between human scorers (98%, 98%, and 94%, respectively). Using SCOPRISM, we replicated the main sleep and sleep-dependent cardiovascular findings of our previous studies. Finally, the cross-laboratory analyses showed that the SCOPRISM algorithm performed well on mouse and rat data. COMPARISON WITH EXISTING METHODS SCOPRISM performed similarly or even better than recently reported algorithms. SCOPRISM is a very simple algorithm, extensively (cross)validated and with the possibility to evaluate its efficacy following a quick and easy visual flow chart. CONCLUSIONS We validated SCOPRISM, a new, automated and open-source algorithm for sleep scoring on a large population of mice, including different mutant strains and on subgroups of mice and rats recorded by independent labs. This algorithm should help accelerate basic research on sleep and integrative physiology in rodents.

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

A different approach to the design of CMOS MAPS has recently been proposed. By exploiting the triple well option of a CMOS commercial process, a deep n-well (DNW) MAPS sensor has been realized with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and a latch. This readout approach beeing compatible with data sparsification will improve the readout speed potential of MAPS sensors. The first protoype chips, realized with STMicroelectronics 130 nm triple well process, proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from 55Fe and electrons from 90Sr. Extensive tests performed to characterize the second generation of the APSEL chips based on the DNW MAPS design are reported. Small 3times3 pixel matrices with full analog output have been tested with radioactive sources to characterize charge collection. Pixel noise equivalent charge (ENC) of 50 e- and signal-to-noise ratio for MIPs of about 14 have been measured. Improved pixel noise and reduced threshold dispersion (about 100 e-) have been measured in the 8times8 matrix with a sequential readout. Based on the new DNW MAPS design a dedicated fast readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels.

Build-up of interference patterns with single electrons

A conventional transmission electron microscope, equipped with a fast recording system able to measure the electron arrival time and the position of single electrons, is used to show the build-up of interference patterns. Two experiments are presented. The first is the electron version of the Grimaldi and Young experiments performed with light, where single electrons strike on an opaque thin wire. Interference fringes are observed in the geometrical shadow of the wire and diffraction effects are clearly displayed at the wire edges. The second, original experiment reports the build-up of two-slit interference patterns with single electrons.