Marco Ho

A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages

A power-efficient 90-nm low-dropout regulator (LDO) with multiple small-gain stages is proposed in this paper. The proposed channel-resistance-insensitive small-gain stages provide loop gain enhancements without introducing low-frequency poles before the unity-gain frequency (UGF). As a result, both the loop gain and bandwidth of the LDO are improved, so that the accuracy and response speed of voltage regulation are significantly enhanced. As no on-chip compensation capacitor is required, the active chip area of the LDO is only 72.5 μm × 37.8 μm. Experimental results show that the LDO is capable of providing an output of 0.9 V with maximum output current of 50 mA from a 1-V supply. The LDO has a quiescent current of 9.3 μA, and has significantly improvement in line and load transient responses as well as performance in power-supply rejection ratio (PSRR).

Dynamic Bias-Current Boosting Technique for Ultralow-Power Low-Dropout Regulator in Biomedical Applications

A dynamic bias-current boosting technique that concurrently enables ultralow-power operation and fast-transient behavior is presented in this brief. It is applied to an ultralow-power output-capacitor-free low-dropout regulator (LDO) to demonstrate the bandwidth extension provided during the transient periods. The proposed LDO is capable of providing 50 mA of output current with a minimum dropout voltage of 0.1 V. The ultralow-power LDO is implemented in a commercial 0.13-μm CMOS process, with power consumption of 1.20 μW only. Experimental results verify that both the load- and line-transient responses of the proposed LDO are significantly improved, and the settling times during load and line transients are shortened by as much as 33 and 3 times, respectively.

Placement constraints in floorplan design

In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like datapath alignment and I/O connection. There are several previous works focusing on some particular kinds of placement constraints. In this paper, we will present a unified method to handle all of them simultaneously, including preplace constraint, range constraint, boundary constraint, alignment, abutment, and clustering, etc., in general, nonslicing floorplans. We have used incremental updates and an interesting idea of reduced graph to improve the runtime of the method. We tested our method using some benchmark data with about 1/8 of the modules having placement constraints and the results are very promising. Good packings with all the constraints satisfied can be obtained efficiently.

A

A cascade structure of six proposed signal-current enhancers is applied to a standard operational transconductance amplifier (OTA) to improve its gain-bandwidth (GBW) product, slew rate (SR), and voltage gain through significant enhancements of the small-signal and transient output currents from the proposed enhancers. The proposed hybrid OTA is implemented in a standard 0.13 μm CMOS technology, with an active chip area of 0.0027 mm2. Working under a 0.7 V supply and as proven by the measurement results, the resultant OTA when driving an output capacitor of 15 nF attained ~100 dB gain, a GBW of 1.46 MHz, and an SR of 0.47 V/μs, consuming only 24 μA of current and requiring no compensation capacitor.

0.7\;\text{V}\;24\;\upmu\text{A}

A single-inductor multiple-output (SIMO) converter with auto-buck-boost feature is presented in this paper. A seamless auto-buck-boost scheme for SIMO dc-dc converter using time-multiplexing control is proposed. Additionally, with the proposed first-order phase-locked loop (FOPLL) and autophase allocation, this circuit solves the problem of unbalanced loadings of different channels, and it also keeps the locking time of the inductor current sufficiently short to minimize average inductor current for attaining higher efficiency. By combining with all channel controllers, FOPLL not only allows fast load-transient response without degrading the power efficiency, but it also reduces controller order of the frequency control loop, attenuates the noise injected from charge pump, and achieves robust stability. The scheme enables the dc-dc converter to operate from wide input and output ranges. Implemented in a 0.35-μm CMOS technology, the chip area is 5000 μm × 1850 μm, including ESD test pads. The switching frequency is fixed at 0.25 MHz. The load-transient response time is less than 100 μs. The proposed converter achieves a peak efficiency of 89% and maximum output power up to 1.46 W with efficiency of 70%.

Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW

A dominant-pole substitution (DPS) technique for low-dropout regulator (LDO) is proposed in this paper. The DPS technique involves signal-current feedforward and amplification such that an ultralow-frequency zero is generated to cancel the dominant pole of LDO, while a higher frequency pole substitutes in and becomes the new dominant pole. With DPS, the loop bandwidth of the proposed LDO can be significantly extended, while a standard value and large output capacitor for transient purpose can still be used. The resultant LDO benefits from both the fast response time due to the wide loop bandwidth and the large charge reservoir from the output capacitor to achieve the significant enhancement in the dynamic performances. Implemented with a commercial 0.18-μm CMOS technology, the proposed LDO with DPS is validated to be capable of delivering 100 mA at 1.0-V output from a 1.2-V supply, with current efficiency of 99.86%. Experimental results also show that the error voltage at the output undergoing 100 mA of load transient in 10-ns edge time is about 25 mV. Line transient responses reveal that no more than 20-mV instantaneous changes at the output when the supply voltage swings between 1.2 and 1.8 V in 100 ns. The power-supply rejection ratio at 3 MHz is -47 dB.

A Single-Inductor Multiple-Output Auto-Buck-Boost DC–DC Converter With Autophase Allocation

An area-efficient cross-coupled voltage doubler (CCVD) with no reversion loss using first-level gate-control mechanism is presented. The proposed design does not require area-consuming resistors or extra power MOSFETs to prevent reversion currents. Through the first-level gate controls, the proposed CCVD is able to use internal nodes to drive the gates of the power MOSFETs without extra buffers, thus further reducing the silicon area and power consumption. The proposed design has been fabricated in a commercial 0.35-μm CMOS technology (VTHN ≈ 0.59 V, VTHP ≈ -0.72 V), with an active area of only 0.49 mm2. Experimental results show that it can achieve a maximum of 96.5% power efficiency value under a supply voltage range of 0.8-1.6 V with a maximum loading current of 30 mA.

A CMOS Low-Dropout Regulator With Dominant-Pole Substitution

This paper presents three different topologies of energy-efficient fast-transient low-dropout regulators (LDOs) for SoC applications. They include: 1) an output-capacitorless LDO with a direct voltage-spike detection circuit, 2) an output-capacitorless 90-nm LDO compensated by a single Miller capacitor, and 3) a power-efficient 90-nm LDO with multiple small gain stages. The LDO designs demonstrate some recently developed circuit techniques to improve both the regulation accuracy and transient performance. Experimental results are included in this paper to verify the achieved performance.

An Area-Efficient 96.5%-Peak-Efficiency Cross-Coupled Voltage Doubler With Minimum Supply of 0.8 V

A single-inductor multiple-output (SIMO) auto-buck-boost dc-dc converter with proposed tail-current control to achieve fast and robust reference tracking of inductor current is proposed in this paper. Moreover, the proposed backward-Vx1 control algorithm and frequency-control loop enable the proposed SIMO dc-dc converter to operate at a fixed switching frequency and achieve high power-conversion efficiency in both the buckdominated and boost-dominated cases. The proposed SIMO auto-buck-boost dc-dc converter has four output channels and is implemented in a standard 0.35-μm CMOS process. Measurement results show that the proposed dc-dc converter achieves a peak efficiency of more than 91% at a total output power of about 0.5 W and load transient response time of less than 80 μs.

Development of energy-efficient fast-transient CMOS low-dropout regulators for SoC applications

A two-stage large-capacitive-load amplifier with multiple cross-coupled small-gain stages is proposed in this paper. The cross-coupled structure of the small-gain stages augments the large-signal responses, providing significant improvement in the effective output-stage transconductance and, hence, the gain- bandwidth product (GBW). Implemented in a standard 0.13-μm CMOS technology and powered by a 0.7 V supply with a current consumption of 20 μA, the proposed amplifier achieves the GBW of 1.17 MHz and the phase margin of 74.8° while driving a capacitive load of 9.5 nF. The average slew rate is 0.3679 V/μs. The on-chip compensation capacitor is only 1.62 pF. The active chip area is 0.0056 mm2.