Yanqi Zheng

A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control

Hysteresis voltage-mode control is a simple and fast control scheme for switched-mode power converters. However, it is well-known that the switching frequency of a switched-mode power converter with hysteresis control depends on many factors such as loading current and delay of the controller which vary from time to time. It results in a wide noise spectrum and leads to difficulty in shielding electro-magnetic interference. In this work, a phase-lock loop (PLL) is utilized to control the hysteresis level of the comparator used in the controller, while not interfering with the intrinsic behavior of the hysteresis controller. Some design techniques are used to solve the integration problem and to improve the settling speed of the PLL. Moreover, different control modes are implemented. A buck converter with proposed control scheme is fabricated using a commercial 0.35-μ m CMOS technology. The chip area is 1900 μm × 2200 μm. The switching frequency is locked to 1 MHz, and the measured frequency deviation is within ±1%. The measured load transient response between 160 and 360 mA is 5 μ s only.

A Single-Inductor Multiple-Output Auto-Buck-Boost DC–DC Converter With Autophase Allocation

A single-inductor multiple-output (SIMO) converter with auto-buck-boost feature is presented in this paper. A seamless auto-buck-boost scheme for SIMO dc-dc converter using time-multiplexing control is proposed. Additionally, with the proposed first-order phase-locked loop (FOPLL) and autophase allocation, this circuit solves the problem of unbalanced loadings of different channels, and it also keeps the locking time of the inductor current sufficiently short to minimize average inductor current for attaining higher efficiency. By combining with all channel controllers, FOPLL not only allows fast load-transient response without degrading the power efficiency, but it also reduces controller order of the frequency control loop, attenuates the noise injected from charge pump, and achieves robust stability. The scheme enables the dc-dc converter to operate from wide input and output ranges. Implemented in a 0.35-μm CMOS technology, the chip area is 5000 μm × 1850 μm, including ESD test pads. The switching frequency is fixed at 0.25 MHz. The load-transient response time is less than 100 μs. The proposed converter achieves a peak efficiency of 89% and maximum output power up to 1.46 W with efficiency of 70%.

A CMOS Low-Dropout Regulator With Dominant-Pole Substitution

A dominant-pole substitution (DPS) technique for low-dropout regulator (LDO) is proposed in this paper. The DPS technique involves signal-current feedforward and amplification such that an ultralow-frequency zero is generated to cancel the dominant pole of LDO, while a higher frequency pole substitutes in and becomes the new dominant pole. With DPS, the loop bandwidth of the proposed LDO can be significantly extended, while a standard value and large output capacitor for transient purpose can still be used. The resultant LDO benefits from both the fast response time due to the wide loop bandwidth and the large charge reservoir from the output capacitor to achieve the significant enhancement in the dynamic performances. Implemented with a commercial 0.18-μm CMOS technology, the proposed LDO with DPS is validated to be capable of delivering 100 mA at 1.0-V output from a 1.2-V supply, with current efficiency of 99.86%. Experimental results also show that the error voltage at the output undergoing 100 mA of load transient in 10-ns edge time is about 25 mV. Line transient responses reveal that no more than 20-mV instantaneous changes at the output when the supply voltage swings between 1.2 and 1.8 V in 100 ns. The power-supply rejection ratio at 3 MHz is -47 dB.

A Single-Inductor Multiple-Output Auto-Buck–Boost DC–DC Converter With Tail-Current Control

A single-inductor multiple-output (SIMO) auto-buck-boost dc-dc converter with proposed tail-current control to achieve fast and robust reference tracking of inductor current is proposed in this paper. Moreover, the proposed backward-Vx1 control algorithm and frequency-control loop enable the proposed SIMO dc-dc converter to operate at a fixed switching frequency and achieve high power-conversion efficiency in both the buckdominated and boost-dominated cases. The proposed SIMO auto-buck-boost dc-dc converter has four output channels and is implemented in a standard 0.35-μm CMOS process. Measurement results show that the proposed dc-dc converter achieves a peak efficiency of more than 91% at a total output power of about 0.5 W and load transient response time of less than 80 μs.

A fixed-frequency auto-buck-boost SIMO DC-DC converter with duty-cycle redistribution and duty-predicted current control

This paper presents a fixed-frequency auto-buck-boost SIMO dc-dc converter with duty-cycle redistribution and duty-predicted current control. The switching sequence of the power transistors in the power stage and the controller design achieve fixed-frequency operation with an optimized duty-cycle allocation, to deal with static and dynamic unbalanced loading conditions of different channels. The proposed control scheme reduces average inductor current for reducing conduction loss and cross regulation during load transients.

Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads

A pseudo three-stage amplifier with large capacitive loads is proposed in this paper. The proposed idea enables pole-relocation such that a single-pole amplifier can be virtually developed. The pole-relocation is done by using the flipped voltage follower to insolate the large parasitic capacitance and the large drain resistance of MOSFET devices. The idea was simulated using the BSIM models of a commercial 0.35-mum CMOS technology. No on-chip capacitor is needed to achieve the stability of the amplifier. The unity-gain frequency of the amplifier based on the proposed technique is 7.3 MHz and the phase margin is 59deg when driving a 500-pF load. When comparing to the Miller-compensated counterpart, the bandwidth improvement is about 52 times. A comparison based on the well-accepted figure of merits (12170, based on the power consumption, and 25420, based on the supply current) is shown.

A 3.3-MHz fast-response load-dependent-on/off-time buck-boost DC-DC converter with low-noise hybrid full-wave current sensor

Abstract A 3.3-MHz current mode control buck-boost DC-DC converter is proposed in this work. Composed of comparator control and load-dependent on/off time modulation technique, the converter can achieve a faster load transient response by reducing the delay from 2.7 μs to 1.5 μs during constant on/off time. Thus, the comparator can take effect faster. To fulfill a fixed frequency operation to reduce electromagnetic interference (EMI), a frequency controller locks the switching frequency to 3.3 MHz. Also, a hybrid full-wave current sensor is proposed to achieve current mode control. The proposed hybrid current sensor inherits good AC performance from a filter-based current sensor and good DC performance from a SenseFET-based one. As a result, state switching between high-side sensing and low-side sensing will not induce large spiking on the current sensor output. Moreover, the DC accuracy of current sensing will not be affected by the DC resistance (DCR) of the inductor.

A digital-control sensorless current-mode boost converter with non-zero error bin compensation and seamless mode transition

A digital-control sensorless current-mode boost DC-DC converter is presented in this paper. By using the proposed sensorless current-mode control, the requirement for implementation of current sensor for conventional current-mode dc-dc converter is relaxed. Moreover, the converter can seamlessly switch between CCM and DCM operation as in conventional current-mode control. With this method, the non-limited-cycle for digital-control current-mode converter is realized. Lower resolution of DPWM can be used to avoid the appearance of limited cycle, regardless of loading condition.

A robust cross-regulation-suppressed single-inductor multiple-output dc-dc converter with duty-regulated comparator control

A robust cross-regulation-suppressed single-inductor multiple-output (SIMO) dc-dc converter with duty-regulated comparator control is proposed. The control scheme effectively combines comparator-based and linear-compensator-based controllers to achieve fast load-transient response and low cross regulation to other output channels simultaneously. The control algorithm does not rely on duty-inductor-current feed-forward which is sensitive to the accuracy of inductor-current sensor. As a result, it can provide robust cross-regulation suppression for a wide range of loading for the SIMO dc-dc converter. Moreover, together with the average-inductor-current control, the proposed control algorithm is suitable for SIMO dc-dc converter which has auto-buck-boost property for each sub-converter, which makes the SIMO converter suitable for dynamic voltage scaling applications.

A 124-dB double-gain-boosted cascode amplifier with 92% rail-to-rail output swing

A CMOS amplifier with 124-dB dc gain and 92% rail-to-rail output swing is proposed in this paper. The proposed amplifier uses double gain-boosting technique, enabling triode-region operation in cascode output stage. The design is fabricated in a commercial 0.35-μm CMOS technology. The active chip area is 84 μm × 170 μm. Experimental results show that with the supplies of ±1 V, the high-gain region is extended beyond -0.93 V and 0.91 V. The unity-gain frequency is about 300 kHz with a phase margin of 65° when driving a loading capacitor of 100 pF. Signal distortion is significant reduced compared to the conventional design due to extension of the high-gain region in the proposed amplifier.