Marco Vigilante

20.10 A 68.1-to-96.4GHz variable-gain low-noise amplifier in 28nm CMOS

To allow a maximum theoretical data-rate of 25Gb/s over a 1km distance using 64QAM, an E-Band system should feature a 20dBm-output-power TX and an RX with 10dB maximum noise figure (NF) over two bands of 5GHz from 71 to 76GHz and 81 to 86GHz [1]. To minimize the NF of a fully integrated RX front-end and to compensate for the low conversion gain and high noise of the following mixer, a broadband LNA with a gain in excess of 20dB showing a flat NF over more than a 15GHz bandwidth is required. Moreover, a variable-gain LNA design would be beneficial to accommodate environmental variability (e.g. atmospherics condition, rain, etc.). Prior works on CMOS car-radar transceivers have shown the feasibility of low-noise amplifiers at 79GHz. However, the bandwidth of these systems is limited to about 10GHz [2,3], which is not enough. This paper presents a 28nm-bulk-CMOS LNA for E-Band applications that employs transformer-based 4th-order inter-stage matching networks to achieve a 29.6dB gain over a 28.3GHz -3dB bandwidth (BW-3dB), resulting in a GBW product in excess of 0.8THz. The gain is variable from 29.6 to 18dB allowing an input-referred 1dB compression point (ICP1dB) that ranges from -28.1dBm at the highest gain to -12.3dBm at the lowest gain. The measured minimum in-band NF is 6.4dB, and the NF varies by less than 2dB from 68.1 to 90GHz. The LNA covers the two bands from 71 to 76GHz and from 81 to 86GHz with an almost uniform gain and NF and with a wide margin over desired specifications to compensate for PVT variations and model inaccuracy.

Analysis and Design of an E-Band Transformer-Coupled Low-Noise Quadrature VCO in 28-nm CMOS

This paper presents an E-band quadrature voltage-controlled oscillator implemented in 28-nm CMOS. Two fundamental oscillators are coupled by means of gate-to-drain transformers to realize accurate quadrature phases and switched coupled inductors are added for tuning extension. Closed-form expressions of the oscillation frequency and the tuning extension design parameters are derived. The time-variant nature of the circuit noise to phase noise (PN) of the presented topology is investigated, resulting in simple design guidelines for optimal design. Based on the proposed techniques, the realized prototype is tunable over two bands of almost 5 GHz each separated in frequency, while occupying only 0.031 mm2. The peak measured PN at 10-MHz offset is -117.7 dBc/Hz from a 72.7-GHz carrier and -110 dBc/Hz from a 88.2-GHz carrier and varies less than 3.5 dB within each band.

An E-Band low-noise Transformer-Coupled Quadrature VCO in 40 nm CMOS

This paper presents a Transformer-Coupled Quadrature VCO (TC-QVCO) designed to achieve low-noise performance at millimeter-wave. The VCO core is implemented combining the tuned-input tuned-output (TITO) oscillator and the Colpitts oscillator, while the coupling is realized by means of transformers, resulting in low noise and accurate quadrature phases. Designed in a 40 nm CMOS process, the TC-QVCO operates between 83.7 GHz and 88.7 GHz (i.e, 5.8% tuning range). Dissipating 28.4 mW from a 0.7 V supply, the measured phase noise is -118.8 dBc/Hz at 10 MHz offset from a 88.7 GHz carrier, resulting in a peak phase-noise FoM of -183.2 dBc/Hz. The I/Q phase error is less than 1.2° over the whole tuning range.

A dual-band E-band quadrature VCO with switched coupled transformers in 28nm HPM bulk CMOS

This paper presents a quadrature VCO (QVCO) that employs gate-to-drain transformers to couple two fundamental oscillators to generate accurate quadrature phases and switched coupled inductors for tuning extension. Thanks to these techniques, it is possible to cover two bands with a single quadrature VCO, without jeopardizing phase noise or demanding extensive silicon area. The oscillator, realized in 28nm HPM bulk CMOS, occupies a core area of only 0.031mm2 and is tunable from 71-to-76GHz and 85.6-to-90.7GHz, resulting in a total tuning range of 9.8GHz. The peak phase noise at 10MHz offset from the carrier is - 117.7dBc/Hz in the lower band and -110dBc/Hz in the higher one and varies less than 3.5dB within each sub-band. The maximum phase error is 1.5° and 3.5° in the lower and higher band respectively.

Multiphase digitally controlled oscillator for future 5G phased arrays in 90 nm CMOS

This paper reports a low noise Digitally Controlled Oscillator (DCO) with multiphase outputs, suitable for next generation phased arrays. The DCO core is implemented using an 8 stage Rotary Traveling Wave Oscillator (RTWO) topology. Simple design equations are presented and insight is given in the layout implementation. Designed in a 90 nm CMOS process, the prototype is tunable from 31.4 to 37 GHz (i.e. 16% tuning range). Drawing 45 mW from a 1.2V supply, the simulated phase noise is −127.3 dBc/Hz at 10 MHz offset from a 34 GHz carrier, resulting in a phase-noise FoM of −181.4 dBc/Hz. Digitally tuned slow wave transmission lines are used to achieve a fine tuning resolution of 1.8 MHz, resulting in a state-of-the-art tuning FoMDT of −187 dBc/Hz.

A 25–102GHz 2.81–5.64mW tunable divide-by-4 in 28nm CMOS

A wideband tunable divide-by-4 is designed and realized in 28nm bulk CMOS. A systematic design methodology to maximize the locking range over power consumption ratio is proposed. The test chip core area is only 25.6×24.8μm2 and measurements repeated over several samples demonstrate an operating frequency range from 25GHz to 102GHz with a maximum power consumption of 5.64mW from a 0.9V supply. The frequency band from 44.3GHz to 90GHz is covered in only three steps with a minimum fractional bandwidth in exceed of 20% and power consumption less than 4.7mW demonstrating the effectiveness of the proposed design techniques.

A 29-to-57GHz AM-PM compensated class-AB power amplifier for 5G phased arrays in 0.9V 28nm bulk CMOS

This paper presents a 29-to-57GHz (65% BW) AM-PM compensated class-AB power amplifier tailored for 5G phased arrays. Designed in 0.9V 28nm CMOS without RF thick top metal, the PA achieves a Psat=15.1dBm±1.6dB and |AM-PM|<1° from 29-to-57GHz, with a peak PAE of 24.2%. Techniques are studied to realize the required load impedance and distortion cancellation over the wide band of operation, while allowing 2-way power combining to further increase the delivered POUT. The very low AM-PM distortion of the realized PA enables up to 10.1, 8.9, 5.9dBm average POUT while amplifying a 1.5, 3, 6Gb/s 64-QAM respectively at 34GHz with EVM/ACPR better than −25dBc/−30dBc, without any digital pre-distortion.

To EVM or Two EVMs?: An Answer to the Question

Error vector magnitude (EVM) is a key indicator of modulated signal quality. It measures how far a transmitted or received constellation point is from its ideal Compared to other system-level specifications such as bit error rate, the EVM contains more information about amplitude and phase distortion and circuit limitations. It is designed to be a measurement of in-band signal quality. This is one of the major reasons why EVM is widely used to quantify the degradation of modulated signals due to circuit impairments, especially for transmitters and including the effects from power amplifiers (PAs). However, there are multiple ways to calculate EVM, and these methods do not provide identical results. Therefore, it is important to be aware of these differences when a comparison with the state of the art is made. For any performance comparison to be valid, it is essential to apply the exact same metric. Otherwise, the comparison is not valid.

5G and E-Band Communication Circuits in Deep-Scaled CMOS

Introduction -- Gm Stage and Passives in deep-scaled CMOS -- Gain-Bandwidth Enhancement Techniques for mm-Wave fully integrated Amplifiers -- mm-Wave LC VCOs -- mm-Wave Dividers -- mm-Wave Broadband Downconverters -- mm-Wave Highly-Linear Broadband Power Amplifiers -- Conclusion.

Gain-Bandwidth Enhancement Techniques for mm-Wave Fully-Integrated Amplifiers

This chapter recalls filter basics and introduces design techniques to achieve gain-bandwidth enhancement and further approach the Bode-Fano limit. A strong focus is put on filter topologies that lead to relatively easy implementation with on-chip components and have shown state-of-the-art performance at mm-Wave.