Patrick Reynaert

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.

A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS

A fully integrated 5.8 GHz Class AB linear power amplifier (PA) in a standard 90 nm CMOS process using thin oxide transistors utilizes a novel on-chip transformer power combining network. The transformer combines the power of four push-pull stages with low insertion loss over the bandwidth of interest and is compatible with standard CMOS process without any additional analog or RF enhancements. With a 1 V power supply, the PA achieves 24.3 dBm maximum output power at a peak drain efficiency of 27% and 20.5 dBm output power at the 1 dB compression point.

A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

A 60-GHz dual-mode power amplifier (PA) is implemented in 40-nm bulk CMOS technology. To boost the amplifier performance at millimeter-wave (mmWave) frequencies, a new transistor layout is proposed to minimize the device and interconnect parasitics while the neutralized amplifier stage is co-optimized with input transformer to improve the power gain and stability. The transformer-based power-combining PA consists of two unit amplifiers, operating in Class AB for better back-off efficiency. To further reduce the power consumption and hence extend battery lifetime, one unit PA is tuned off in low-power mode. A switch is used to short the output of this non-operating unit PA to reduce the combiner loss and improve the efficiency. The PA achieves a measured saturated output power (PSAT) of 17.0 dBm (12.1 dBm) and 1-dB compressed power (P1dB) of 13.8 dBm (9.1 dBm) in the high-power (low-power) mode. The power-added efficiencies (PAEs) at PSAT and P1dB are 30.3% and 21.6% respectively for the high-power mode. Compared to Class A, the PA operating in Class AB shows 5.3% improvement in measured PAE at P1dB with no compromise in linearity. The PA with the power combiner only occupies an active area of 0.074 mm 2. The reliability measurements are also conducted and the PA has an estimated lifetime of 80613 hours.

Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank

A 60 GHz voltage-controlled oscillator with an inductive division LC tank has been designed in 90 nm CMOS. The analysis of the oscillator shows that the presence of higher harmonics, the capacitance nonlinearity and the very high K VCO are critical for the phase noise performance of oscillators. Therefore, a pseudo-differential amplifier is employed in this design because of its high linearity. Furthermore, the proposed inductive division reduces the phase noise by increasing the signal amplitude across the varactor, without affecting the operation mode of the cross-coupled pair transistors. It also helps to increase the tuning range by isolating the varactor from the parasitic capacitances of the transistors and interconnects. The mm-wave oscillator is fabricated in a 90 nm CMOS technology. Under 0.7 V supply, the oscillator achieves a tuning range from 53.2 GHz to 58.4 GHz, consuming 8.1 mW. At 58.4 GHz, the phase noise is -91 dBc/Hz at 1 MHz offset. Under 0.43 V supply, the oscillator achieves a tuning range from 58.8 to 61.7 GHz. At 61.7 GHz, the phase noise is -90 dBc/Hz @1& MHz offset with a power consumption of only 1.2 mW.

A 60-GHz Outphasing Transmitter in 40-nm CMOS

This paper presents the analysis, design, and implementation of a 60-GHz outphasing transmitter in 40-nm bulk CMOS. The 60-GHz outphasing transmitter is optimized for high output power and peak power-added efficiency (PAE) while maintaining sufficient linearity. The chip occupies an active area of 0.33 mm2 and consumes 217 mW from a 1-V supply voltage, delivering 15.6-dBm linear output power with 25% PAE (PA). It achieves a 500-Mb/s 16QAM modulation with 12.5-dBm average output power and 15% average efficiency (PA) at an EVM of -22 dB. Mismatch compensation and phase correction are applied to further improve the average output power and efficiency by about 1.6 dB and 4%, respectively.

Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques

State-of-the-art synthesis methods for microwave passive components suffer from the following drawbacks. They either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high, or they fully depend on electromagnetic (EM) simulations, with a high solution quality but are too time consuming. To address the problem of combining high solution quality and good efficiency, a new method, called memetic machine learning-based differential evolution (MMLDE), is presented. The key idea of MMLDE is the proposed online surrogate model-based memetic evolutionary optimization mechanism, whose training data are generated adaptively in the optimization process. In particular, by using the differential evolution algorithm as the optimization kernel and EM simulation as the performance evaluation method, high-quality solutions can be obtained. By using Gaussian process and artificial neural network in the proposed search mechanism, surrogate models are constructed online to predict the performances, saving a lot of expensive EM simulations. Compared with available methods with the best solution quality, MMLDE can obtain comparable results, and has approximately a tenfold improvement in computational efficiency, which makes the computational time for optimized component synthesis acceptable. Moreover, unlike many available methods, MMLDE does not need any equivalent circuit models or any coarse-mesh EM models. Experiments of 60 GHz syntheses and comparisons with the state-of-art methods provide evidence of the important advantages of MMLDE.

A 60-GHz CMOS VCO Using Capacitance-Splitting and Gate–Drain Impedance-Balancing Techniques

The design and measurement of a 60-GHz 90-nm CMOS voltage-controlled oscillator is presented. To reduce the power consumption and to improve the phase-noise performance, a capacitance-splitting and a gate-drain impedance-balancing techniques, which are realized with an inductive divider, are proposed. With these techniques, the size of the cross-coupled pair is reduced. Analysis of the proposed techniques shows that the transistor g m generation efficiency is improved and the oscillator noise factor is reduced. Moreover, the tank loaded quality factor is increased by balancing impedance levels across the transistor terminals. The 60-GHz oscillator was fabricated in a 90-nm CMOS technology. Under 0.6-V supply, the oscillator achieved a tuning range from 61.1 to 66.7 GHz, consuming only 3.16 mW. At 64 GHz, the phase noise is -95 dBc/Hz at 1-MHz offset.

A state-space behavioral model for CMOS class E power amplifiers

Class E amplifiers are imposed by time-domain constraints. This makes the design of such amplifiers more difficult than other types of amplifiers. This paper presents a new method to analyze class E power amplifiers using state-space equations. A description by these equations makes it possible to find the correct initial conditions that leads to the steady-state solution of the amplifier. Furthermore, it is possible to derive the power balance of the power amplifier based on its state-space equations. The presented method has shown to be very valuable when designing switched power amplifiers. Furthermore, the method can also be applied for power amplifiers that do not fulfill the class E switching conditions.

A 120GHz 10Gb/s phase-modulating transmitter in 65nm LP CMOS

This paper presents a 120GHz fully integrated 65nm low power (LP) CMOS transmitter that achieves data rates above 10Gb/s. At these high frequencies an extremely high bandwidth is available. This allows multi-gigabit-per-second communication which provides an answer to the ever-increasing demand for higher data rates in wireless systems. However, wideband modulation of a 120GHz signal in 65nm LP CMOS is a challenge.

A 0.54 THz Signal Generator in 40 nm Bulk CMOS With 22 GHz Tuning Range and Integrated Planar Antenna

This work presents the design and measurements of a 0.54 THz signal generator implemented in a 40 nm bulk CMOS technology. An LC-VCO operating at 180 GHz is connected to a nonlinear buffer, which is designed to generate the wanted third harmonic at 540 GHz. The third harmonic is coupled via a transformer to the output. The developed techniques are implemented on two different chips: one with a probe pad for on-wafer measurements and one with an on-chip planar dipole. The measured peak output power using a WR-1.5 probe is -31 dBm at 543 GHz, for 16.8 mW of dc power consumption. By changing value of the parasitic I-MOS varactors of the LC-VCO (“parasitic tuning”), the output frequency can be tuned from 561.5 to 539.6 GHz, resulting in a 21.9 GHz tuning range, which is the highest reported so far for CMOS THz oscillators. The 3-dB output bandwidth is 5.5 GHz. The 540 GHz signal generator with on-chip antenna is used for THz imaging without the use of substrate or focusing lenses, demonstrating some of the capabilities of CMOS for low-cost, mass-produced THz imagers.