Marek J. Patyra

Digital fuzzy logic controller: design and implementation

In this paper, various aspects of digital fuzzy logic controller (FLC) design and implementation are discussed, Classic and improved models of the single-input single-output (SISO), multiple-input single-output (MISC), and multiple-input multiple-output (MIMO) FLCs are analyzed in terms of hardware cost and performance. A set of universal parameters to characterize any hardware realization of digital FLCs is defined. The comparative study of classic and alternative MIMO FLCs is presented as a generalization of other controller configurations. A processing element for the parallel FLC architecture realizing improved inferencing of MIMO system is designed, characterized, and tested. Finally, as a case feasibility study, a direct data stream architecture for complete digital fuzzy controller is shown as an improved solution for high-speed, cost-effective, real-time control applications.

Impact of local interconnects on timing and power in a high performance microprocessor

In nanometer technologies, local interconnects are believed to cause a major impact on timing and power in VLSI circuits. To assess the impact of the interconnects on timing and power in a real high performance microprocessor design in a quantitative manner, this article presents results from an extensive study carried out on RTL-to-layout synthesized blocks in a 45-nm technology core. The study shows that the interconnects in these blocks account for 30% of the cycle time, on an average, on the worst internal timing paths and contribute nearly one-third to the power dissipation. This points to severity of impact due to the interconnects in todays high performance designs.

Hardware implementations of digital fuzzy logic controllers

In this paper, various implementation issues of digital fuzzy logic controllers (FLC) are investigated. Models of the single-input-single-output (SISO) and multiple-input-multiple-output (MIMO) FLCs are analysed in terms of hardware implementation. Classis and alternative implementation of inference engines are presented. Direct Data Stream (DDS) FLC architecture is shown as an improved solution for high-speed, realtime control applications.

Synthesis of current mode building blocks for fuzzy logic control circuits

Since the introduction of the first digital-based fuzzy logic controller chip, efficient hardware design of fuzzy logic control systems (FLCS) has drawn substantial attention. The interest in fuzzy logic hardware systems is motivated by the desperate need to provide fast fuzzy logic-based systems capable of operating in real time process control conditions. Fuzzy logic hardware implementation problems can be classified into two basic categories: the digital approach and the analog approach. The digital approach was originated by Togai and Watanabe who developed the first digital fuzzy logic-based inference engine chip. However, the digital approach to the fuzzy logic hardware implementation seems to be less efficient in contrast to analog, especially when the complexity and speed of a control problem are crucial. The transformation of a real-world fuzzy data into a binary format requires tremendous processing power that must be provided in the real time. Therefore, the analog solution offers a sufficient strategy to solve fuzzy logic control problems in dedicated hardware. Recently, successful implementation of current mode fuzzy logic controller developed in CMOS technology was reported. This approach starts with the theoretic framework for fuzzy set operations that leads to the coherent representation of the fuzzy inference operations, including fuzzification and defuzzification. The proposed approach, utilizing the control strategy proposed by Mamdani, concentrates on the algebraic correctness and elegance. It is algebraically effective but it lacks the current mode circuit implementation insight. This drawback motivated the presented research. This paper presents a graph-oriented approach to the synthesis of fuzzy logic building blocks. The framework for synthesis of current-mode fuzzy logic circuits is derived and the graph representations of basic building blocks are developed. These blocks comprise the bounded difference circuit, the absolute difference circuit, the minimum circuit, the maximum circuit, and the membership function circuit. Thereafter, the circuit implementations are analyzed and the circuit implementation issues related to the accuracy of the fuzzy operations are discussed.<<ETX>>

Embedded deterministic test points for compact cell-aware tests

The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×-4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.

Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor

In nanometer technologies, local interconnects are believed to cause a major impact on timing and power in VLSI circuits. To assess the impact of the interconnects on timing and power in a real high performance microprocessor design in a quantitative manner, this article presents results from an extensive study carried out on RTL-to-layout synthesized blocks in a 45-nm technology core. The study shows that the interconnects in these blocks account for 30% of the cycle time, on an average, on the worst internal timing paths and contribute nearly one-third to the power dissipation. This points to severity of impact due to the interconnects in todays high performance designs.

A degenerated fuzzy-number processing system based on artificial neural networks

In this paper, a degenerated fuzzy-number processing system based on artificial neural networks (ANNs) is introduced. The digital representation of fuzzy numbers is assumed, where the universe of discourse is discretized into n equally divided intervals. It is proposed that fuzzy-number processing be performed in two basic stages. The first stage performs the retrieval of fuzzy data consisting of degenerated fuzzy numbers and the second stage performs the desired fuzzy operations on the retrieved data. The method of incomplete fuzzy-number retrieval is proposed based on an ANN structure that is trained to estimate the missing membership function values.

High-Performance Digital Defuzzification and Defuzzifier Circuit

This article discusses the design and development of a high-speed digital defuzzifier circuit that can be used as a stand alone chip associated with a conventional or fuzzy logic processor or as a macrofunctional block built into the fuzzy logic processor chip. As a case example, the presented defuzzifier circuit is designed to have 64*5 bit input data bus and 32 bit output data bus. The choice of the input/output data bus size is arbitrary and the design can be modified according to the users needs. The output data bus, representing the scalar output value, is organized in such a way that the first 8 bits represent the real number and the remaining 24 bits represent its fraction. The accuracy of the defuzzification equals 11256. The defuzzifier is pipelined to assist in higher throughput, and therefore, for a used technology n-well 1.2-μm CMOS its maximum frequency of operation is 100 MHz. This means that as soon as the pipeline is filled, the defuzzifier reads 64*5 bit fuzzy input and generates the 32-bit scalar output every 10 ns. This defuzzifier, as an element of the fuzzy logic controller design, was simulated at the postlayout stage of development.

Architecture for event-driven intelligent fuzzy controller

The authors describe a model for synchronous finite state machines based on fuzzy logic. Such finite state machines can be used to build both event-driven time-varying rule-based systems and the control unit section of a fuzzy logic computer. The architecture of a pipelined intelligent fuzzy controller is presented, and the linguistic model is represented by an overall fuzzy relation stored in a single rule memory. A VLSI integrated circuit implementation of the fuzzy controller is suggested. At a clock rate of 30 MHz, the controller can perform 3 M fuzzy logical inferences per second (FLIPS) on multidimensional fuzzy data.<<ETX>>

On New Test Points for Compact Cell-Aware Tests

Test points are known to improve the fault coverage in BIST applications. This article discusses a new class of test points used to improve the ATPG pattern count in designs that employ embedded deterministic test.