Elham K. Moghaddam

Embedded deterministic test points for compact cell-aware tests

The introduction of FinFET technology has accelerated the adoption of patterns that target cell internal defects such as cell-aware tests. Even though cell-aware tests can replace stuck-at and transition patterns from the screening point of view, we have to address the increase in test data volume. This combined with the growing gate counts enabled by new technology nodes is driving the need for even greater compression levels. In this paper, we present a novel test points technology designed to reduce deterministic pattern counts for cell-aware tests. The technology is based on identification and resolution of conflicts across internal signals allowing ATPG to significantly increase the number of faults targeted by a single pattern. Experimental results on a number of industrial designs with test compression demonstrate that the proposed test points are effective in achieving, on average, a 3×-4× multiplicative increase in compression for 1-cycle and 2-cycle cell-aware patterns.

Isometric Test Data Compression

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Isometric test compression with low toggling activity

The paper presents a novel test data compression scheme. The invention follows from a fundamental observation that in a typical test cube only a small portion of the specified positions are necessary to detect a fault, and most of the remaining ones have many alternatives. The necessary assignments are used to form test templates which both control a decompressor to guarantee the necessary assignments and guide ATPG to find alternative assignments to produce highly compressible test cubes. The proposed approach synergistically elevates compression ratios to values typically unachievable through conventional reseeding-based solutions. It also reduces, in a user-controlled manner, switching rates in scan chains with minimal hardware modification. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein.

Power Aware Embedded Test

In this paper we examine several embedded low power test schemes that we have proposed over the last few years. These solutions are aimed at reducing the switching activity during all scan-based test operations, particularly including those developed for BIST or deployed to perform on-chip test data compression.

Design for low test pattern counts

This paper presents a new method to design digital circuits for low pattern counts, one of the key factors shaping cost-effective VLSI test schemes. The method identifies the largest conflicts between internal signals that prevent efficient test compaction in ATPG. These locations are modified by inserting conflict-reducing test points (CRTP) to significantly reduce the ATPG-produced pattern counts. Experimental results obtained for large industrial designs with on-chip test compression demonstrate, on average, 3x - 4x reduction in stuck-at and transition patterns and 3x shorter ATPG times.

Minimal area test points for deterministic patterns

Conflict-aware test points, introduced recently, facilitate significant reductions in deterministic test pattern counts. However, dedicated flip-flops driving control points increase test logic area. This paper presents a method to minimize silicon area needed to implement conflict-aware test points by reusing functional flip-flops as drivers of control points. Conflict analysis is applied during the test point selection process, and ATPG verification is run for every potential candidate. Experimental results show that functional flip-flops can be reused as drivers for more than 90% of the control points with the average of 5% penalty in pattern count increase as compared to methods using only dedicated flip-flops. After replacing dedicated flip-flops with functional flip-flops, conflict-aware test points can still achieve remarkable pattern count reductions.

On New Test Points for Compact Cell-Aware Tests

Test points are known to improve the fault coverage in BIST applications. This article discusses a new class of test points used to improve the ATPG pattern count in designs that employ embedded deterministic test.

Test point insertion in hybrid test compression/LBIST architectures

Logic built-in self-test (LBIST), originally introduced for board, system, and in-field tests, is now being increasingly used with on-chip test compression. This hybrid approach allows LBIST to become a complementary solution for in-system test, where high quality, low power, low silicon area, and most importantly short test application time are key factors affecting ICs that are targeted for safety-critical and automotive systems. Test points are common in BIST-ready designs where they play a key role in reducing both test application time given a test coverage goal and the overall silicon overhead so that one can get a desired coverage with the minimal number of patterns. Unfortunately, these test points are typically dysfunctional when enabled in an ATPG-based test compression mode. Similarly, test points used to reduce ATPG-based test pattern counts cannot guarantee desired random testability. Incompatibility of both types of test points has motivated research presented in this paper. We present a novel hybrid test point technology designed to both reduce deterministic pattern counts and improve fault detection likelihood by means of the same minimal set of test points. Experimental results obtained for large industrial designs illustrate feasibility of the proposed hybrid test points and are reported herein.

On Test Points Enhancing Hardware Security

Recent reverse-engineering attempts to steal a competitive design intellectual property (IP) or to identify the device technology in order to counterfeit integrated circuits (ICs) have raised serious concerns in the IC design community. This paper demonstrates that test points - industry-proven design-for-test technology used to enhance the overall design testability - can also be deployed in the mission mode to obfuscate the circuits structure, and thus to improve the hardware security against reverse engineering, IC cloning, and IP theft. In particular, it is shown how test points can facilitate the hiding of design functionality from adversaries. As a result, not only the overall design testability is improved, but also effective protection against reverse engineering and other forms of attacks is ensured.