Marek Syrzycki

Commercial CMOS fabricated integrated dynamic thermal scene simulator

The authors report a prototype integrated dynamic thermal scene simulator chip, consisting of a 2*2 array of integrated thermal pixels. The chips were fabricated using commercial CMOS processes. The micromachining process needed to create the thermally isolated structure is introduced as a maskless postprocessing step. The thermal pixel and the control electronics are designed as a module for an easy implementation of the array. Test results indicate that the pixels have a thermal time constant of 5 ms and are capable of producing an infrared output of apparent radiometric temperatures in excess of 600 degrees C and color temperatures of at least 500 degrees C. The control electronics is capable of switching within 900 ns, enabling the addressing of multiple pixels within the 200 Hz frame time required for a typical dynamic thermal scene simulation.<<ETX>>

Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays

An analytical design methodology for continuous-time (CT) bandpass (BP) /spl Sigma//spl Delta/ modulators is presented. Second- and fourth-order tunable continuous time BP /spl Sigma//spl Delta/ modulator design equations are presented. A novel /spl Sigma//spl Delta/ loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the methodology is confirmed by mixed-signal behavioral simulations.

Gas detector with low-cost micromachined field ionization tips

This letter describes a low-cost fabrication of field ionization tips for gas detection application. The method addresses some of the most important aspects of micro gas detector technology; namely, manufacturing cost, sensitivity and reproducibility. The tips were designed and fabricated with standard microfabrication technologies: thermal oxidation, wet chemical etching and sputtering. However, the major achievement is the use of a low-resolution mask to position the tips very closely to a second electrode in a self-aligned process. In our investigation, the vaporized CH/sub 3/COOH was selected as the sample gas to measure the detector sensitivity. The minimum-measured sensitivity of the detector is 14 ppm and this was accomplished at an operating voltage of only 5 V.

Current-mode CMOS adders using multiple-valued logic

In this paper we report on initial development stages of two designs of current-mode multiple-valued logic (CMMVL) adders utilizing a positive digit (PD) number representation. The first design is the adder cell that uses the radix-2 algorithm and seven levels of current, fabricated in 0.8 /spl mu/m CMOS technology, with a unit current step of 12 /spl mu/A. The second design is a 4-digit decimal adder that uses a standard algorithm for adding decimal numbers represented by 10 current levels, with a unit current step equal to 1 /spl mu/A, fabricated in 1.5 /spl mu/m CMOS technology. The adder requires 4 input terminals compared to 10 terminals necessary for the same function implemented in binary logic.

CMOS photodetector with built-in light adaptation mechanism

Abstract This paper reports research results on a new class of silicon hotodetectors with built-in light adaptation mechanisms. Previously used devices feature a limited dynamic range which is much smaller than a range of light intensity present in our environment. Intelligent vision systems functioning similarly to human vision systems require new photodetectors with abilities not only to cover wider dynamic range, but also able to accomplish background adaptation and dark adaptation mechanisms similar to those existing in human retina. The proposed class of devices uses the same silicon structure operating in two or more operating modes of different sensitivity, with light-controllable switching between different modes. The measurements conducted on CMOS photodetectors fabricated in the 3 μm CMOS technology show that the new photodetectors have a dynamic range increased by at least two orders of magnitude and feature limited power consumption, which is especially attractive for large area transducer systems.

A wafer scale visual-to-thermal converter

Wafer scale transducer arrays (WSTAs) containing multi-transducer arrays combined with processing circuits are produced using a combination of CMOS technology, silicon micromachining and laser interconnection techniques. A prototype wafer scale visual-to-thermal converter is being developed to convert a visual scene to thermal scene with the same resolution. The basic array is composed of transducer pixels, which combine photodetectors and thermal emitters as transducers, together with signal conditioning and control circuitry. The WSTA redundancy approach is driven by regularity in transducer location and emphasizes local over global transducer sparing.<<ETX>>

Modifications of a Dynamic-Logic Phase Frequency Detector for extended detection range

This paper presents two modified architectures of a Dynamic-Logic Phase Frequency Detector (PFD) which eliminate the blind-zone problem. The PFDs have linear phase-frequency characteristics for the input phase difference outside of the blind-zone, and constant phase-frequency characteristics for the phase difference inside the blind-zone. The proposed new PFD architectures extend the detection range and eliminate the polarity reversal issue of the output. The circuits have been designed in 0.13µm CMOS technology and the simulation results have demonstrated a detection range improvement in comparison to previously existing solutions.

A tool for automated analog CMOS layout module generation and placement

Layout design is a very important step of the analog CMOS IC design flow. Good layout quality featuring low susceptibility to digital noise and low sensitivity to process variation requires layout designers with significant expertise. The layout optimization process needs new CAD tools that will quickly generate multiple versions of analog CMOS IC layouts for parasitic extraction and post-layout simulation. We propose a new CAD tool that will produce analog CMOS layout modules in a given CMOS process. Multiple use of the tool with different control parameters results in obtaining several versions of CMOS layout modules of a single circuit. These layouts can be used for post-layout simulation and layout optimization. This paper presents the tools architecture and examples of its use for analog CMOS layout design.

Fabrication of affordable metallic microstructures by electroplating and photoresist molds

Electroforming processes such as electroplating was used in conjunction with photoresist mold to fabricate surface and substrate micromachined structure. Gold, gold alloys and nickel and nickel-iron alloys were used as structural material in this technique. In case of surface micromachining free standing, cantilevers, bridges and linear and torsional comb drives on silicon substrate were fabricated, whereas in case of substrate micromachined magnetic actuators were fabricated using the above mentioned technology. The thickness of metallic microstructures varied from 8 /spl mu/m to 20 /spl mu/m. This presentation discusses the technology we have developed in our laboratory to fabricate affordable metallic microstructures, as well as presenting functional devices we have built to demonstrate the potential of this technology.

VLSI implementation of receptive fields with current-mode signal processing for smart vision sensors

Most of the early vision processes in vertebrate vision systems can be modelled by receptive fields in the retina. Building silicon retina ICs has been attempted in the past, but they have not reached a satisfactory conclusion due to technology constraints. Targeting a wafer-size smart vision sensor, we focus in this paper on researching the VLSI implementation of different receptive fields with dedicated functions. The microelectronic receptive field (MERF) is defined as a functional block of the larger system, performing a preprogrammed operation on visual input signals. The main component of MERFs are analog processors operating in current domain that use current signals from photodetectors to produce desired image processing function and to convert their outputs into frequency mode signals. Results from VLSI chips with various integrated implementations of receptive fields are presented.