Kris Iniewski

A CMOS IR-UWB Transceiver Design for Contact-Less Chip Testing Applications

This paper presents a novel CMOS impulse radio (IR) ultra-wide-band (UWB) transceiver system design for future contact-less chip testing applications using inductive magnetic coupling as wireless interconnect. The proposed architecture is composed of a simple and robust design of a Gaussian monocycle impulse generator at the transmitter, a wideband short-range on-chip transformer for data transmission, and a gm-boosted common-gate low-noise amplifier in the UWB receiver path. SpectreRF post-layout simulation with a 90-nm CMOS technology shows that the transceiver operates up to a 5 Gb/s data rate, and consumes a total of 9 mW under a 1-V power supply.

A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops

This paper presents a general ring oscillator circuit topology for high speed operation, multiphase output and wide range tuning. The topology uses sub-feedback inverters to construct a fast loop for long chain ring oscillator to achieve high speed. The operating frequency of the ring oscillator is directly proportional to the transconductance (G/sub m/) of sub-feedback inverters which can be controlled with an external voltage. Both single-ended and differential controlled voltage and inverter stages can be used. A quadrature output ring oscillator based on three-stage sub-feedback loops is designed and fabricated in a 0.5 /spl mu/m CMOS process for a 1.25 GHz clock recovery application. The circuit operates from 400 MHz up to 2 GHz, and consumes 3 mW at 1.25 GHz with 3.3 V power supply.

Analysis of error control code use in ultra-low-power wireless sensor networks

High-speed wireless sensor networks are currently being considered for a variety of communication application such as environmental, medical, industrial or security scenarios. For increased transmission rates given the limited embedded battery lifetime, ultra-low-power circuitry is needed in the sensor and processors. Much research is being undertaken in these different areas at the device, circuit, system and network levels Although using error control coding (ECC) potentially reduce the required transmit power for reliable communication, higher decoder complexity increases the required processing energy. The above tradeoff is explored in this paper to find when use of ECC results in more power-efficient systems. Several recently implemented decoders are analyzed, comparing both analog and digital implementations. The four most energy efficient decoders are analog decoders. The best analog decoder becomes energy-efficient at about 1/4 the distance of the best digital implementation

Ultra-low power 90nm 6T SRAM cell for wireless sensor network applications

This paper presents a comparative study of leakage reduction techniques applied to a 90 nm 6T SRAM to find an optimal design for ultra-low power wireless sensor applications. A 4-Kb SRAM implemented with the proposed techniques has a leakage as low as 26.5 nA in the idle mode, a 189times improvement over a memory without applying such techniques

A Low Power CMOS Transmitter Design for IR-UWB Communication Systems

A low power CMOS impulse-based transmitter with on-off keying (OOK) modulation scheme, for ultra-wideband (UWB) impulse radio (IR) system has been designed and laid out in a standard TSMC 0.18 mum CMOS technology. A novel design of Gaussian mono-pulse generator employing simple and robust first-derivative capacitive current-voltage characteristic has been presented. On-chip pulse shaping using an LC Band-Pass Filter (BPF) is developed to meet the Federal Communications Commission (FCC) spectrum requirement. The post-layout simulation results of the proposed UWB transmitter are analyzed. A Gaussian mono-pulse of less than 100 ps falling/rising time with a 130 mVpp amplitude is obtained, at a clock frequency of 500 MHz. The total power dissipation of the transmitter is 1.2 mW with only 316 muW consumed by impulse generator. The output of the transmitter before antenna is 48 mVpp under a 1.2 V power supply.

Semiconductor controlled rectifier (SCR) electrostatic discharge (ESD) protection devices in submicron CMOS technology

Multiple designs of silicon controlled rectifier (SCR) devices as major electrostatic discharge (ESD) protection circuits in 0.35 micron CMOS technology are investigated to provide better insight into their operation. They are also compared with the conventional CMOS ESD protection circuits to investigate possible advantages in smaller silicon area, discharging paths with lower ON resistance and lower holding voltages. The I-V characteristics of designed and fabricated SCRs have been tested. Testing results allows proper tune-up of computational models such as lumped-element models and 2D device models for future use in simulation of I/O pads with ESD protection circuits. High voltage ESD testing using human body model (HBM) were also conducted revealing that designed structures are able to withstand the stress of 1 kV.