Marek Wegrzyn

The application of reconfigurable logic to controller design

Abstract This paper presents a framework that performs the programmable logic synthesis of rule-based descriptions of concurrent controllers. These descriptions can be obtained from several specification models of those controllers (for example, Control Interpreted Petri net, Grafcet or the IEC 1131-3 Sequential Function Chart). The internal description, in the form of symbolic conditional decision rules, is then transformed into a format that is accepted by standard FPLD and FPGA simulators and synthesisers, for example OrCAD or VHDL. The concurrent state machine model of the logic controller is verified using the well-developed Petri-net theory, and then it is translated through automated processes into a selected FPGA specification format, for example the Xilinx netlist format (XNF). This paper presents part of a broad project in the field of hardware/software co-design. The main purpose is to develop different implementations of controllers using a simple, standard and well-known design methodology like SFC (Grafcet) or Petri nets. The paper deals exclusively with the design of FPGA-based controllers.

Implementation of safety critical logic controller by means of FPGA

Abstract In the paper, a synthesis method of logic controllers for safety critical systems into field programmable logic is presented. The specification of the system in the form of symbolic, if-then or if-then-else conditional decision rules is used for directly mapping to netlist format, or transformed into a HDL format that is accepted by standard FPGA simulators and synthesis tools. In addition, models of Logic Controllers are verified using the well-developed Petri net theory, and then they are translated through automated processes into selected FPGA specification format.

Petri net-based specification, analysis and synthesis of logic controllers

The logic control program is usually specified by drawing the Petri net in terms of interface with the electro-mechanical devices and the environment of the system. In such case it is not immediately evident that the control system behaves in a satisfactory way. Industrial engineers prefer frequently a form of specification, like interpreted Petri Net, sequential function chart (SFC), Grafcet or Grafchart. On the other hand, some popular techniques are informal and do not provide means to validate the design. In the paper, modelling, analysis and synthesis of logic controller described by Petri nets is presented. Additional, the use of design/CPN system for modelling, testing and analysis of logic controllers described by means of coloured, interpreted Petri nets is shown. The proposed methods are especially useful in designing of industrial application specific logic controller (ASLC) with FPGA.

Design of Digital Systems and Devices

Logic design of digital devices is a very important part of the Computer Science. It deals with design and testing of logic circuits for both data-path and control unit of a digital system. Design methods depend strongly on logic elements using for implementation of logic circuits. Different programmable logic devices are wide used for implementation of logic circuits. Nowadays, we witness the rapid growth of new and new chips, but there is a strong lack of new design methods. This book includes a variety of design and test methods targeted on different digital devices. It covers methods of digital system design, the development of theoretical base for construction and designing of the PLDbased devices, application of UML for digital design. A considerable part of the book is devoted to design methods oriented on implementing control units using FPGA and CPLD chips. Such important issues as design of reliable FSMs, automatic design of concurrent logic controllers, the models and methods for creating infrastructure IP services for the SoCs are also presented.The editors of the book hope that it will be interesting and useful for experts in Computer Science and Electronics, as well as for students, who are viewed as designers of future digital devices and systems.

Hardware-efficient matrix inversion algorithm for complex adaptive systems

This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively small device as Xilinx Spartan3 XC3S1000, a matrix size up to 23 × 23 can be implemented, having a matrix inversion computation time of 253μs. Accuracy results compared to floating point computation and an estimation of required clock cycles as a function of matrix size are analyzed.

Design of Reconfigurable Logic Controllers from Petri Net-based specifications

Abstract The paper promotes to construct a synthesizable VHDL model from a graphical representation of Petri Net. The VHDL code provides a clear semantics of graphically designed reconfigurable logic controller and serves as reference model for eventual further optimization efforts. It is considered that automatically generated array structure of logic controller is optimized for synthesis by professional tools. The most useful aspect for presented purposes is the ability to execute a VHDL behavioral specification closely related with array-based implementation. Even if the final implementation is not optimized during the logic synthesis process, it is compact, easy to modify and efficient.

Hardware implementation of real-time Extreme Learning Machine in FPGA

Extreme Learning Machine (ELM) on-chip learning is implemented on FPGA.Three hardware architectures are evaluated.Parametrical analysis of accuracy, resource occupation and performance is carried out. Display Omitted Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforward Neural Networks that provides an effective solution for classification and prediction problems. Its hardware implementation is an important step towards fast, accurate and reconfigurable embedded systems based on neural networks, allowing to extend the range of applications where neural networks can be used, especially where frequent and fast training, or even real-time training, is required. This work proposes three hardware architectures for on-chip ELM training computation and implementation, a sequential and two parallel. All three are implemented parameterizably on FPGA as an IP (Intellectual Property) core. Results describe performance, accuracy, resources and power consumption. The analysis is conducted parametrically varying the number of hidden neurons, number of training patterns and internal bit-length, providing a guideline on required resources and level of performance that an FPGA based ELM training can provide.

Partial reconfiguration of compositional microprogram control units implemented on FPGAS

Abstract The method of partial reconfiguration of Compositional Microprogram Control Units implemented on FPGAs is proposed. The method is based on the swapping of the content of Control Memory while the rest of the system is not modified. Such approach permits to decrease the size of a bit-stream that is sent to the device. Therefore time needed for device configuration is shorter. Proposed solution is much more safe due to less errors that can occur during reconfiguration of FPGAs. An example of proposed method application is discussed. The researches conducted by authors have shown that proposed method permits to decrease the size of a bit-stream that is sent to the device in comparison with traditional method even up to 95%.

Modelling and synthesis of automata in HDLs

In the paper digital modelling and synthesis of automata in Hardware Description Languages is described. There is presented different kinds of automata and methods of realization using languages like VHDL and Verilog. Basic models for control units are: Finite State Machine (FSM), Algorithmic State Machine (ASM) and Linked State Machine (LSM). FSM, ASM and LSM can be represented graphically, which would help a designer to visualize and design in a more efficient way. On the other hand, a designer needs a fast and direct way to convert the considered designs into Hardware Description Language (HDL) codes for simulation and analysis it for synthesis and implementation.

PETRI NET DECOMPOSITION APPROACH FOR PARTIAL RECONFIGURATION OF LOGIC CONTROLLERS

Abstract In the paper design method of Reprogrammable Logic Controllers oriented on partial reconfiguration is presented. The Controller is specified by Interpreted Petri net. The Petri net model is decomposed onto a set of State Machine (SM) subnets. Each subnet is modelled using Verilog, and then all subnets are implemented using Field Programmable Gate Arrays (FPGAs). The novel capability of the method is the opportunity for dynamic change of the FPGA configuration with a portion of the original bitstream. Such approach is necessary when a transmission channel for a new configuration is a bottleneck.