Marek Wojcikowski

A field programmable analog array for CMOS continuous-time OTA-C filter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5/spl times/8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade.

FPGA-Based Real-Time Implementation of Detection Algorithm for Automatic Traffic Surveillance Sensor Network

This paper describes the FPGA-based hardware implementation of an algorithm for an automatic traffic surveillance sensor network. The aim of the algorithm is to extract moving vehicles from real-time camera images for the evaluation of traffic parameters, such as the number of vehicles, their direction of movement and their approximate speed, using low power hardware of a sensor network node. A single, stationary, monochrome camera is used, mounted at a location high above the road. Occlusions are not detected, however simple shadow and highlight elimination is performed. The algorithm is designed for frame-rate efficiency and is specially suited for pipelined hardware implementation. The authors, apart from the careful selection of particular steps of the algorithm and the modifications towards parallel implementation, also proposed novel improvements such as backgrounds’ binary mask combination or non-linear functions in highlight detection, resulting in increasing the robustness and efficiency of hardware realization. The algorithm has been implemented in FPGA and tested on real-time video streams from an outdoor camera.

Multiple output differential OTA with linearizing bulk-driven active-error feedback loop for continuous-time filter applications

A CMOS circuit realization of a highly linear multiple-output differential operational transconductance amplifier OTA has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active-error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1dB at power consumption of 276µW from 3.3V supply. As an example, both single output and dual differential OTAs are used to design third-order elliptic low-pass filters. The cut-off frequency of the filters is 1MHz. The power consumption of the OTA-C filter utilizing the dual output differential OTA is reduced to 1.24mW in comparison to 2.2mW consumed by the single output differential OTA-C filter counterpart. Copyright

A CMOS field programmable analog array and its application in continuous-time OTA-C filter design

A general configurable analog block (CAB) is presented, which consists of the programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A prototype 5/spl times/8 CAB array has been fabricated. The chip has also been configured to realize a programmable OTA-C filter. From the simulated and measured results it has been found that filters with frequencies from several kHz to a few MHz can be realized based on the proposed CAB and FPAA.

An intelligent image processing sensor - the algorithm and the hardware implementation

This paper describes the idea and the implementation of the robust algorithm dedicated to extraction of moving vehicles from real-time camera images for the evaluation of traffic parameters, such as the number of vehicles, their direction of movement and their approximate speed. The authors, apart from the careful selection of particular steps of the algorithm towards hardware implementation, also proposed novel improvements, resulting in increasing the robustness and the efficiency. A single, stationary, monochrome camera is used, simple shadow and highlight elimination is performed. The occlusions are not taken into account, due to placing the camera at a location high above the road. The algorithm is designed and implemented in pipelined hardware in FPGA, therefore high frame-rate efficiency has been achieved. The possible applications of the proposed algorithm and its implementation are in the area of intelligent image processing sensors in low-power, cost-effective sensor network applications, i.e. for detecting the moving vehicles on the road.

Multi-core processor system for real-time image processing in embedded computer vision applications

This paper describes the idea of the multi-core programmable cores architecture for real-time image processing in embedded applications. The authors propose the architecture of a simple 8-bit processor core dedicated to low and intermediate level image operations. Several cores are connected to a common, 128-bit wide data bus by multiplexes and their operation is synchronized. The image data on the data bus is processed in parallel by all the processor cores. Each core realizes its own part of the image processing algorithm, what significantly improves the frame rate of the whole system. Apart from a low-level image processing, such as background subtraction, moving object extraction or geometrical transformation of the image, also higher level information can be processed and analysed, i.e. object indexing, blob size and shape estimation or basic trajectory analysis. The system consisting of 9 processor cores has been practically realized in FPGA hardware and verified. The assembler has also been written to provide the tool for software development. Comparing to the typical hardware approach, the proposed idea is very flexible and enables the realization of a wide range of low and intermediate level image processing algorithms.

Support for Employees with ASD in the Workplace Using a Bluetooth Skin Resistance Sensor–A Preliminary Study

The application of a Bluetooth skin resistance sensor in assisting people with Autism Spectrum Disorders (ASD), in their day-to-day work, is presented in this paper. The design and construction of the device are discussed. The authors have considered the best placement of the sensor, on the body, to gain the most accurate readings of user stress levels, under various conditions. Trial tests were performed on a group of sixteen people to verify the correct functioning of the device. Resistance levels were compared to those from the reference system. The placement of the sensor has also been determined, based on wearer convenience. With the Bluetooth Low Energy block, users can be notified immediately about their abnormal stress levels via a smartphone application. This can help people with ASD, and those who work with them, to facilitate stress control and make necessary adjustments to their work environment.