Stanislaw Szczepanski

A field programmable analog array for CMOS continuous-time OTA-C filter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5/spl times/8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade.

Design of highly linear tunable CMOS OTA for continuous-time filters

An analytical method based on the standard square-law metal-oxide-semiconductor (MOS) modeling for the design of highly linear, fully differential complementary metal-oxide-semiconductor (CMOS) operational transconductance amplifier (OTA) is presented. The proposed circuit implementation combines a cross-coupled quad cell and a source-coupled differential pair, as well as the current mirror technique in the output stage. As a result, improved linearity of the developed OTA over the large tuning range is obtained. SPICE simulations show that for 0.5-/spl mu/m HP AMOS14TB process (MOSIS) with a 2.5 V power supply, total harmonic distortion (THD) at 2.5V/sub pp/ is less than 0.5%. The dynamic range is equal to 76 dB at power consumption 5.7 mW. The alternative OTA structures are also discussed and compared to the basic version; for this circuit THD at 2.5V/sub pp/ is less than 0.2%, however, the circuit is much more sensitive to the transistor mismatch. As an example, the OTA is used to design a third-order elliptic lowpass filter in the high-frequency range. The cutoff frequency of the filter is tunable in the range of 4.6-29.6 MHz.

A general framework for evaluating nonlinearity, noise and dynamic range in continuous‐time OTA‐C filters for computer‐aided design and optimization

Efficient procedures for evaluating nonlinear distortion and noise valid for any OTA-C filter of arbitrary order are developed based on matrix description of a general OTA-C filter model. Since those procedures use OTA macromodels, they allow us to obtain the results significantly faster than transistor-level simulation. On the other hand, the general OTA-C filter model allows us to apply matrix transforms that manipulate (rescale) filter element values and/or change topology without changing its transfer function. Due to this, the proposed procedures can be used in direct optimization of OTA-C filters with respect to important characteristics such as noise performance, THD, IM3, DR or SNR. As an example, a simple optimization procedure using equivalence transformations is discussed. An application example of the proposed approach to optimal block sequencing and gain distribution of 8th order cascade Butterworth filter is given. Accuracy of the theoretical tools has been verified by comparing to transistor-level simulation results and to experimental results. Copyright

An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is implemented in 0.35 μm CMOS technology, and contains a 64 × 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s.

Dynamic range comparison of voltage-mode and current-mode state-space G/sub m/-C biquad filters in reciprocal structures

This paper is concerned with a dynamic range (DR) comparison of reciprocal state-space G/sub m/-C biquad filters based on adjoint transformation. A detailed analytical description of general G/sub m/-C filters (i.e., containing both grounded and floating capacitances) of arbitrary order is derived and discussed. In particular, we investigate the relationships between the state matrices of voltage- and current-mode filters. Based on the earlier results of Groenewold (1991), the general DR formulas for both types of the state-space G/sub m/-C filters are given. Finally, a DR comparison of selected second-order G/sub m/-C filters of both modes as well as verification of the theoretical results based on the SPICE simulations is performed.

A linear CMOS OTA for VHF applications

The design of a linear, fully-balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with improved gain and very wide bandwidth is described. It uses a cross-coupled, two-differential-pair transconductor together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated DC-gain enhancement is obtained without any bandwidth limitation. SPICE simulation results show THD<1% at 1.9 V/sub p-p/ with dynamic range equal to 63 dB at a power consumption of 2.7 mW from a single 5-V supply. Application to a lowpass filter in the VHF range is presented as an example, assuming implementation in a standard 2 /spl mu/m CMOS process (MOSIS). The cutoff frequency of the filter is tunable in the range of 8.3-50.0 MHz.

1.2V low-power four-quadrant CMOS transconductance multiplier operating in saturation region

The paper describes a simple CMOS technique for realizing a linear, low-voltage, low-power, four-quadrant transconductance multiplier based on MOS transistors working in saturation region. The proposed circuit has been developed and simulated using standard 0.35/spl mu/m AMS process. SPICE simulations show that the total harmonic distortion (THD) at 0.3V/sub pp/@1MHz applied to Y input is -70.5dB with 0.1V DC voltage applied to X input. Input referred noise equals 0.6/spl mu/V/Hz/sup 1/2/ which results in the dynamic range of the circuit equal to 52dB. Power consumption is 0.05mW from a single 1.2V supply. An example of application the CMOS multiplier as a modulator is presented.

Linearized CMOS OTA using active-error feedforward technique

Highly linear operational transconductor amplifier (OTA) is developed, using CMOS differential pair transconductors in an active-error feedforward linearization configuration. As a result, improved linearity of the differential-input two-output OTA is obtained. SPICE simulations show that for the circuit working with a /spl plusmn/1.25 V power supply, total harmonic distortion (THD) for f = 1 MHz at 0.4V/sub pp/ (0.8/sub pp/) is less than -72 dB (-60 dB) in comparison to -35 dB (-20 dB) without linearization. Moreover, the input voltage range of linear operation is increased by more than 300%. Power consumption of the overall circuit is 0.94 mW.

Implementation of AES algorithm resistant to differential power analysis

This paper describes differential power analysis (DPA) of encryption algorithms hardware implementations. Proposed DPA-resistant design method combines power equalization for synchronous and combinatorial circuits. AES algorithm has been implemented in Xilinx Spartan II-E field programmable gate array (FPGA) device using the standard and DPA-resistant methods. XPower tool has been introduced to collect power traces for DPA. Results show that the standard AES implementation can be broken using DPA in N=2000 encryption operations. At the same time DPA of modified AES implementation for N=2000 encryption operations does not show any correlation between power consumption and the cipher key.

VHF fully-differential linearized CMOS transconductance element and its applications

The design of a fully-differential highly linear, voltage-tunable CMOS transconductance element with improved gain performance and wide bandwidth is described. A negative resistance load (NRL) technique for compensation of the parasitic output resistance of the transconductor circuit is employed without requiring extra internal nodes. Owing to this, the DC-gain enhancement is obtained without any penalty in the bandwidth. An improved transconductance circuit is presented with its application to third-order transconductance-capacitor (C) filter in the very high frequency (VHF) range assuming implementation in a standard 3 /spl mu/m CMOS process. The cutoff frequency of the filter is tunable in the range of 9.7-48.4 MHz. The filter total harmonic distortion (THD) is lower than -50 dB for an output signal up to 1V/sub p-p/ at 5 MHz frequency has been predicted via SPICE simulation.<<ETX>>