Margaret Simmons-Matthews

Reliability Assessment of Through-Silicon Vias in Multi-Die Stack Packages

A thermo-mechanical reliability study of through-silicon vias (TSVs) is presented in this paper. TSVs are used to interconnect stacked dies to achieve 3-D packages. As the core of the TSV contains high coefficient of thermal expansion (CTE) copper surrounded by low-CTE SiO2 and Si materials, the thermo-mechanical reliability of TSVs is a concern. When dies with such TSVs are stacked and packaged, the presence of additional structures and associated materials could introduce different thermo-mechanical concerns compared with free-standing wafers. This paper presents 3-D finite-element models for studying the thermo-mechanical stresses in TSVs in free-standing wafers and in stacked dies, which are packaged. Warpage measurements have been used to validate the finite-element modeling approach. The results from the finite-element models show that the TSV stresses in a packaging configuration are typically lower than the TSV stresses in a free-standing wafer configuration. In addition, it is seen that the microbumps connecting adjacent dies experience high magnitude of inelastic strain, indicating that such locations are of reliability concern.

Thermo-mechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps

Through-silicon via (TSV), being one of the key enabling technologies for 3D system integration, is being used to interconnect 3D vertically stacked devices, such as logic, memory, sensors, and actuators that are fabricated on separate wafers and then interconnected by either wafer-to-wafer or chip-to-wafer methods. However, thermo-mechanical analyses on TSVs are limited, and most of the existing studies focus on the thermo-mechanical analysis of TSVs in a freestanding wafer, rather than in an integrated package. In this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in a 3D integrated package which contains stacked dice with TSVs, inter-chip microbumps, overmold, and underfilled solder bumps, and an organic substrate. Models show that the stresses in the TSV under packaging configuration could be generally lower than the stresses in the TSV in a free-standing wafer. Also, the models show that the high-strain region switches from TSV corners to microbumps.

Reliable Design of TSV in Free-Standing Wafers and 3D Integrated Packages

Through-silicon via (TSV), being one of the key enabling technologies for three dimensional (3D) Integrated Circuit (IC) stacking, silicon interposer technology, and advanced wafer level packaging (WLP), has attracted tremendous interest throughout the semiconductor industry. However, limited work addresses TSV reliability issue, and most of the existing reliability studies focus on the thermo-mechanical performance of TSVs in a free-standing wafer, rather than in an integrated package. In this paper, three-dimensional thermomechanical Finite-Element (FE) models with TSVs in both free-standing wafers and 3D integrated packages have been built and analyzed. In addition, Design of Experiments (DOE) based approach has been used to understand the effect of various parameters. Results show that the selection of underfill materials between stacked dies is the most dominating design factor for TSV/microbump reliability.Copyright