Maria K. Michael

Exact path delay fault coverage with fundamental ZBDD operations

We formulate the path delay fault (PDF) coverage problem as a combinatorial problem that amounts to storing and manipulating sets using a special type of binary decision diagrams, called zero-suppressed binary decision diagrams (ZBDD). The ZBDD is a canonical data structure inherently having the property of representing combinational sets very compactly. A simple modification of the proposed basic scheme allows us to increase significantly the storage capability of the data structure with minimal loss in the fault coverage accuracy. Experimental results on the ISCAS85 benchmarks show considerable improvement over all existing techniques for exact PDF grading. The proposed methodology is simple, it consists of a polynomial number of increasingly efficient ZBDD-based operations, and can handle very large test sets that grade very large number of faults.

Exploring the public-private sector wage gap in European countries

We estimate the public-private sector pay gap for 27 European countries, using the 2008 EU SILC. The coefficients of conditional (on personal and job characteristics) public sector controls give a first impression on wage differences, while decompositions into explained and unexplained components (also accounting for selectivity) allow for a more complete analysis, which helps to identify possible causes of the gap. Regional patterns exist. Separate subsample decompositions based on age, education, gender and occupation, provide interesting insight regarding the pay structure of each country. Quantile decomposition analyses show that the public-private pay gap is, generally, negatively related to income quantiles.JEL classificationJ31, J45, J48

Function-based compact test pattern generation for path delay faults

We present a function-based nonenumerative automatic test pattern generation (ATPG) methodology for detecting path delay faults (PDFs). The proposed technique consists of a number of topological circuit traversals during each a linear number of Boolean functions is generated per circuit line. From each such function we derive a test that detects many PDFs. The two major strengths of the approach, that stem from the function-based formulations used, are very compact test sets, and scalability in test efficiency. The performance of an implementation based on binary decision diagrams is evaluated and compared with existing compact methods to demonstrate the superiority of the proposed method.

Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques

This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

Accelerating Diagnosis via Dominance Relations between Sets of Faults

A new way of fault collapsing for effect-cause diagnosis is presented. In contrast to existing dominance-based methods which operate on a pair of faults, the proposed method operates on pairs of sets of faults. The impact of the proposed method is evaluated with respect to effect-cause diagnosis. Experimental results show that the proposed collapsing methods can reduce the diagnostic simulation time on an average of 31% when compared to the existing techniques

ATPG tools for delay faults at the functional level

We propose and evaluate two frameworks for functional level ATPG for delay faults in combinational circuits. Although functional delay fault models have been recently proposed [9, 13, 10], no systematic methodologies for ATPG have been presented in the literature. The proposed frameworks apply to any proposed fault model, and utilize established techniques such as Reduced Ordered Binary Decision Diagrams (ROBDDs) and Boolean Satis ability (SAT).

Efficient deterministic test generation for BIST schemes with LFSR reseeding

We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses binary decision diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes

Identification of critical primitive path delay faults without any path enumeration

It has been previously shown that in order to guarantee the temporal correctness of a circuit, only the primitive path delay fault set needs to be tested. However, as in the case of the traditional and simpler path delay fault model, the number of possible faults can be exponential to the circuit size and, therefore, it is only practical to consider the set of critical faults. This work defines critical primitive path delay faults and presents an exact algorithm to identify them, using zero-suppressed binary decision diagrams and newly introduced operators necessary for handling multiple path delay faults. We report the number of critical primitive path delay faults for various criticality thresholds under the bounded delay model. The results indicate that only a small, but still necessary, number of multiple (primitive) faults, which escape testing under the singly testable fault criterion, must be considered in order to guarantee the timing correctness of the circuit.1

DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems

As technology scales deep into the sub-micron regime, transistors become less reliable. Future systems are widely predicted to suffer from considerable aging and wear-out effects. This ominous threat has urged system designers to develop effective run-time testing methodologies that can monitor and assess the systems health. In this work, we investigate the potential of online software-based functional testing at the granularity of individual microprocessor core components in multi-core systems. While existing techniques monolithically test the entire core, our approach aims to reduce testing time by avoiding the over-testing of under-utilized units. To facilitate fine-grained testing, we introduce DaemonGuard, a framework that enables the real-time observation of individual sub-core modules and performs on-demand selective testing of only the modules that have recently been stressed. The monitoring and test-initiation process is orchestrated by a transparent, minimally-intrusive, and lightweight operating system process that observes the utilization of individual datapath components at run-time. We perform a series of experiments using a full-system, execution-driven simulation framework running a commodity operating system, real multi-threaded workloads, and test programs. Our results indicate that operating-system-assisted selective testing at the sub-core level leads to substantial savings in testing time and very low impact on system performance.

Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors

We present a novel methodology for protecting incore microprocessor memory arrays from Multiple Bit Upsets (MBUs). Recent radiation studies in modern SRAMs demonstrate that up to 55% of Single Event Upsets (SEUs) due to alpha particle or neutron strikes result in MBUs. Towards suppressing these MBUs, methods such as physical interleaving or periodic scrubbing have been successfully applied to caches. However, these methods are not applicable to in-core, high-performance Content-Addressable Memories (CAM) arrays, due to computational complexity, high delay and area overhead, and lack of information redundancy. To this end, we propose a cost-effective method for enhancing in-core memory array resiliency, called Vulnerability-based Interleaving (VBI). VBI physically disperses bit-lines based on their vulnerability factor and applies selective parity to these lines. Thereby, VBI aims to ensure that an MBU will affect at most one critical bit-field, so that the selective parity will detect the error and a subsequent pipeline flush will remove its effects. Experimental results employing simulation of realistic MBU fault models on the instruction queue of the Alpha 21264 microprocessor in a 65nm process, demonstrate that a 30% selective parity protection of VBI-arranged bit-lines reduces vulnerability by 94%.