Stelios Neophytou

Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques

This work presents two new methods for the generation of test sets with a small number of specified bits. Such type of test sets have been proven beneficial to a large number of test-related applications such as deterministic BIST, low power testing and test set enrichment. The first technique is static, since it considers an initial test set which attempts to relax via test replacement with tests of similar coverage but with fewer specified bits. The second technique is dynamic; it generates a test set from a zero base using a hierarchical fault-compatibility algorithm. Both methods are applicable to any enumerative fault method (linear to the circuit size). The experiments performed using the stuck-at fault model demonstrate the superiority of the proposed methods over comparable existing techniques, in reducing the total number of specified bits per generated test set. The applicability of the generated relaxed test sets is demonstrated for one, out of the many, possible applications, that of deterministic test set embedding. A general framework that integrates the proposed relaxation methods in two popular LFSR-based test set embedding schemes (full and partial reseeding), along with a systematic exploration of related parameters, is proposed. The obtained results show significant reductions in seed storage requirements.

Efficient deterministic test generation for BIST schemes with LFSR reseeding

We propose a novel method for generating test patterns that can be encoded efficiently using reseeding of LFSR-based schemes for hybrid BIST. Our focus is to reduce the number of deterministic tests while keeping their overall number of specified bits small and, thus, reduce the storage requirements for the LFSR seeds. The proposed solution is based on test function manipulation and generates a compact test set in which individual tests have a high number of unspecified bits. The method uses binary decision diagrams (BDDs) and a modified version of the min-cost max-matching problem on graphs. The obtained experimental results clearly demonstrate the impact of the proposed ATPG algorithm in reducing the on-chip seed storage, when combined with the considered BIST schemes

Identification of critical primitive path delay faults without any path enumeration

It has been previously shown that in order to guarantee the temporal correctness of a circuit, only the primitive path delay fault set needs to be tested. However, as in the case of the traditional and simpler path delay fault model, the number of possible faults can be exponential to the circuit size and, therefore, it is only practical to consider the set of critical faults. This work defines critical primitive path delay faults and presents an exact algorithm to identify them, using zero-suppressed binary decision diagrams and newly introduced operators necessary for handling multiple path delay faults. We report the number of critical primitive path delay faults for various criticality thresholds under the bounded delay model. The results indicate that only a small, but still necessary, number of multiple (primitive) faults, which escape testing under the singly testable fault criterion, must be considered in order to guarantee the timing correctness of the circuit.1

On the Relaxation of n-detect Test Sets

While defect oriented testing in digital circuits is a hard process, detecting a modeled fault more than one time has been shown to result in high defect coverage. Previous work shows that such test sets, known as n-detect test sets, are of increased quality for a number of common defects in deep sub-micron technologies, n-detect test generation methods usually produce fully specified test patterns. This limits their usage in a number of important applications such as low power test and test compression. This work proposes a systematic methodology for identifying a large number of bits that can be unspecified in an n-detect test set, while preserving the n-detection property, in contrast to any other existing test set relaxation method. The experimental results demonstrate that the number of specified bits in, even compact, n- detect test sets can be significantly reduced without any impact on the n-detect property.

Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits

Identification of bits that do not necessarily have to be specified in a test set can be beneficial to a number of applications, including low power test, test set encoding and embedding, and test set enriching with n-detect or other fault types properties. This work presents a new method for generating tests containing only a small number of specified bits, while keeping the number of total tests small. The method relies on finding a large number of faults that can be detected by a single test (compatible faults) with a small number of specified bits. Both the total number of specified bits in the test set as well as the number of specified bits per test are minimized. The obtained experimental results show that the proposed methodology can generate compact test sets with an average of 60% of unspecified bits, outperforming existing methods that consider this problem.

Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement

A method to implicitly derive all tests for each transition fault under established fault-sensitization criteria is presented. The derived quality test functions are enhanced in three different ways to derive better quality test sets. One enhancement restricts fault sensitization along critical subcircuits whose paths have long delays under a fixed-delay model. Another manipulates the functions to generate compact test sets. The last one enriches the test set with additional test vectors so that transition faults are tested through several activation and propagation paths without path enumeration. Experimental results demonstrate the effectiveness of deriving such enhanced test functions

Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning

Testing modeled faults multiple times has been shown to increase the likelihood of a test set to detect non-modeled faults, either static or dynamic, when compared to a single detect test set. Test sets that guarantee detecting every modeled fault with at least n different tests are known as n-detect test sets. Moreover, recent investigations examine how different the various tests for a fault should be, in order to further increase their ability in detecting defects. This work proposes a new test generation methodology for multiple-detect (including n-detect) test sets that increases their diversity in terms of the various fault propagation paths excited by the different tests. Specifically, the various tests per modeled fault are guaranteed to propagate the fault effect via different propagation paths. The proposed method can be applied to any linear, to the circuit size, static or dynamic fault model for multiple fault detections, such as the stuck-at or transition delay fault models, and avoids any path or path segment enumeration. Experimental results show increased numbers of propagation paths and non-modeled fault coverages when compared to traditional n-detect test sets.

Scalable parallel fault simulation for shared-memory multiprocessor systems

Multicore architectures can significantly accelerate the performance of well-established design and test automation processes, provided that the underlying process is scalable with respect to the system on which it is executed. In this work we concentrate on fault simulation and propose a new parallel process for shared-memory multicore systems, capable of maintaining its scalability as the number of processing cores utilized increases. In order to maximize parallelization, the method utilizes a simple, non-optimized single thread simulation process, which allows for high degrees of freedom to be exploited by three different and combined dimensions of parallelism. Simulation data is distributed to the available cores in a balanced fashion in order to favor speed-up over single-core executions and, ultimately, scalability. The experimental results show that the proposed approach achieves high speed-up rates which, in contrast to comparable state-of the-art methods, increase monotonically with the number of cores demonstrating a highly scalable solution.

Two New Methods for Accurate Test Set Relaxation via Test Set Replacement

This paper presents two different techniques for relaxing a given test set by maximizing the number of unspecified bits in the test set, without compromising the fault coverage or increasing the test set size. The first method replaces each pattern in the test set with another targeting as few faults as necessary. The second method iterates among faults and enforces detection of a fault only by the test resulting in the largest specified bits reduction. Experimental results show increased reduction rates, even when the input test set has been compacted or already contains unspecified bits, when compared to existing methods. The effectiveness of the proposed methods is demonstrated for two popular test set embedding schemes, using the obtained test sets.

Utilizing shared memory multi-cores to speed-up the ATPG process

A new test generation methodology is proposed that takes advantage of shared memory multi-core systems. Appropriate parallelization of the main steps of ATPG allocates resources in order to minimize workload duplication and multi-threading race contention, often encountered in parallel implementations. The proposed approach ensures that the obtained acceleration grows linearly with the number of processing cores and, at the same time, keeps the test set size close to that obtained by serial ATPG. The experimental results demonstrate that the proposed methodology achieves higher degree of speed-up than comparable state-of-the-art multi-core based tools, while maintains similar test set sizes.