Mariaconcetta Canino

Effects of heating ramp rates on the characteristics of Al implanted 4H–SiC junctions

The role of the heating rate in the postimplantation annealing process of SiC was investigated. Structural and electrical properties of an Al+ implanted junction in n-type 4H–SiC were studied for a 30min annealing at 1600°C in argon atmosphere and changing the heating rate between 7 and 40°C∕s. With the increasing of the heating rate the surface roughness increases, but the electrical performance of the devices improves. In particular, the faster ramp-up rate reduces the sheet resistance of the implanted layer of about 40% with respect to the slowest process and significantly reduces the leakage current of the diodes.

Current Analysis of Ion Implanted p+/n 4H-SiC Junctions: Post-Implantation Annealing in Ar Ambient

An n-type 8° off-axis <0001> 4H-SiC epitaxial wafer was processed. The n-type epilayer had doping and thickness of, respectively, ~3 × 1015 cm-3 and ~5 μm. p+/n diodes with not terminated junctions were constructed by a selective area implantation process of 9.2 × 1014 cm-2 Al+ ions at 400°C. The diodes had areas in the range 2×10-4 -1×10-3 cm2. The Al depth profile was 6×1019 cm-3 high and 164 nm thick. The post implantation annealing process was done in a high purity Ar ambient at 1600°C for 30 min. The diode current-voltage characteristics were measured in the temperature range 25-290°C. Statistics of 50-100 measurements per device type were done. The fraction of diodes that could be modeled as abrupt junctions within the frame of the Shockley theory decreased with increasing area value, but was always > 75%. The ideality factor was > 2 only at temperatures > 200°C and bias values < 1 V. The leakage current was extremely weak and remained of the order of 10-9 Acm-2 at 70°C and 500 V reverse bias. 4% of the diodes reached the theoretical voltage breakdown that was 1030 V. The surface roughness of un-implanted and implanted regions after diode processing was, respectively, 2 nm and 12 nm.

Correlation between Current Transport and Defects in n+/p 6H-SiC Diodes

This paper reports on the defects created in a 6H-SiC p-type substrate by a process of ion implantation and a quite low temperature annealing (1300 °C), suitable for the realization of the source/drain regions of a MOSFET because it does not give rise to step bunching phenomena. Current voltage measurements showed the presence of a group of diodes featured by excess current. The effects of defects under the implanted layer on the transport properties of the diodes were investigated by DLTS: four hole traps were detected in all the measured diodes; besides, a broadened peak around 550 K was detected in the diodes that show excess current.

Ion Implanted p + /n 4H-SiC Junctions: effect of the Heating Rate during Post Implantation Annealing

Structural, morphological and electrical characteristics of Al-implanted p+/n 4H-SiC diodes are compared for the same implantation process and post implantation annealing with identical stationary and cooling cycles but different heating velocity. Al + ions were implanted at 400°C, with energies in the range 250-350 keV and total fluence of 1.2×10 15 cm −2 . Post implantation annealing processes were done at 1600°C for 30 min with a constant heating velocity in the range 7 – 40°C/sec and an abrupt cooling cycle. Gas in the annealing ambient was high purity Ar. The Al depth profile of annealed and as implanted samples were equal except for concentrations below 10E17 cm −3 where the former profiles showed a diffusion tail. With the increase of the heating velocity of the post implantation annealing process, sheet resistance of the Al implanted layer and diode leakage currents decrease while the surface roughness increases.

Ar Annealing at 1600°C and 1650°C of Al+ Implanted p+/n 4H-SiC Diodes: Analysis of the J-V Characteristics Versus Annealing Temperature

We report on the electrical characterization of Al+ implanted p+/n 4H-SiC diodes via a planar technology. Hot implantation at 400°C and post implantation annealing at 1600°C and 1650°C in high purity Argon ambient were done for the realization of p+/n diodes. The current voltage characteristics of the p+/n diodes and the resistivity of the implanted layer were measured at room temperature. The majority of the 136 measured diodes had a turn on voltage of 1.75 V for both annealing temperatures. The 1600°C annealed diodes showed an almost exponential forward characteristic with ideality factor equal to 1.4, an average reverse leakage current density equal to (4.8 ± 0.1)×10-9 A/cm2 at –100 V, and a break down voltage between 600 and 900V. The 1650°C annealed diodes often had forward “excess current component” that deviates from the ideal forward exponential trend. The average reverse leakage current density was equal to (2.7 ± 0.5)×10-8 A/cm2 at –100 V, and the breakdown voltage was between 700 and 1000V, i.e. it approached the theoretical value for the epitaxial 4H-SiC layer.

Ni-Silicide Contacts to 6H-SiC: Contact Resistivity and Barrier Height on Ion Implanted n-Type and Barrier Height on p-Type Epilayer

Recently Ni/SiC contacts have been studied in order to achieve very low contact resistivity (rc) values on n-type SiC. In this work contact resistivity values of Ni-silicide contacts to n-type ion implanted 6H-SiC are analyzed aiming at extracting the Schottky Barrier Height (SBH). The n-type ion implanted 6H-SiC specimens were annealed at 1300, 1500, 1650°C for 20 min in a high purity Ar ambient. The rc values have been extracted from Transmission Line Method (TLM) measurements in the range of temperatures 25-290°C. The rc values are in the range 1-5×10-5 Wcm2 depending on the annealing temperature. The SBH fBn has been extracted by exploiting the dependence of the contact resistivity on the temperature. By using the field emission model, the value obtained for fBn on our samples is in the range 1.1-1.3 eV depending on the annealing temperature. The SBH on p-type 6H-SiC has been evaluated on Schottky diodes by means of both IV and C-V measurements. A value of qfBp= (1.75±0.05) eV has been obtained on p-type SiC through the C-V method. The average SBH extracted from I-V data collected at room temperature is (1.19±0.03) eV and this value increases as a function of the temperature until (1.50±0.01) eV at 290°C. Differences between values of SBH extracted from I−V and from C−V measurements are explained in terms of inhomogeneous barrier height

Analysis of the Electrical Activation of P+ Implanted Layers as a Function of the Heating Rate of the Annealing Process

The surface morphology and the electrical activation of P+ implanted 4H-SiC were investigated with respect to annealing treatments that differ only for the heating rate. P+ implantation was carried out in lightly doped n-type epitaxial layers. The implantation temperature was 300 °C. The computed P profile was 250 nm thick with a concentration of 1×1020 cm-3. Two samples underwent annealing at 1400 °C in argon with different constant ramp up rates equal to 0.05° C/s and 40 °C/s. A third sample underwent an incoherent light Rapid Thermal Annealing (RTA) at 1100 °C in argon before the annealing at 1400 °C with the lower ramp rate. The ramp up of the RTA process is a few hundred degrees per second. Atomic Force Microscopy (AFM) micrographs pointed out that the surface roughness of the samples annealed at 1400 °C increases with increasing heating rate and that the critical temperature for surface roughening is above 1100 °C. Independently on the annealing cycle, Scanning Capacitance Microscopy (SCM) measurements showed that the P profiles are uniform over the implantation thickness and have plateau concentration around 9×1018 cm-3 in all the implanted samples. The fraction of P atoms activated as donors is 13% of the total implanted fluence.

n+/p Diodes Realized in SiC by Phosphorus Ion Implantation: Electrical Characterization as a Function of Temperature

n+/p diodes have been realized by 300°C phosphorus ion implantation and subsequent annealing at 1300°C. An electrical characterization of the devices as well as a study of the defects introduced by the implantation process has been made. I-V measurements pointed out that the diodes maintain a good rectifying behavior up to 737K. DLTS analyses detected the presence of three traps, T2, T3 and T4, which are not due to the implantation process, and a high energy trap, T5, that could be related to the surface states at the Ni/SiC interface.