Marie-Lise Flottes

High-level synthesis for easy testability

This paper presents an attempt towards design quality improvement by incorporation of testability features during datapath high-level synthesis. This method is based on the use of hardware sharing possibilities to improve the testability of the circuit without a time consuming re-synthesis process. This is achieved by incorporating test constraints during register allocation and interconnect network generation. The main features of this method are: a test analysis at the behavioral level rather than at a structural one; the non limitation on the behavioral descriptions (loops, control constructs are supported); and the optimized test area overhead and CPU time compared to standard approach. The method was applied to several benchmarks resulting in easily testable designs for almost the same area costs as the original (without testability) designs.<<ETX>>

Remote Labs for Industrial IC Testing

This paper deals with the remote access to an Integrated Circuits (ICs) Automated Test Equipment (ATE) for both educational and engineering purposes. This experience was initiated in 1998 in the context of a French network (CNFM) in order to provide a distant control to industrial equipment to academic and industrial people. The actual shared resource is a Verigy V93K System-on-Chip (SoC) tester platform. The cost of such equipment is close to 1 million dollar, without taking into account the maintenance and attached human resources expenses to make it work properly daily. Although the sharing of such equipments seems to be obvious for education, the French experience is quite a unique example in the world. The paper introduces the context of industrial IC testing and justifies the introduction of labs in Electrical Engineering curricula. Practical information regarding IC testing and network setup for remote access are detailed, together with lab contents.

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS

Bulk Built-In Current Sensors (bbicss) were introduced to detect the anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. To date, the experimental testing of only one bbics architecture was reported in the scientific bibliography. It reports an unexpected weakness in its ability to monitor nmos transistors. Based on experimental measures, we propose an explanation of this weakness and also the use of triple-well cmos to offset it. Further, we introduce a new bbics architecture well suited for triple-well that offers high detection sensitivity and low area overhead.

A successful distance-learning experience for IC test education

The paper describes an original educational experience that has been set by French universities to respond to IC manufacturer needs for electronics engineers having a double design and test competence. In each microelectronics academic center, students may be trained in the field of IC testing using real industrial up-to-date test resources. This is made possible by the concept of distributed remote access the authors have developed. In place of having some substandard test tools located in several university centers, it has been chosen to create a unique test center (the so-called CRTC) equipped with a high performing up-to-date ATE representative of real industrial test tools. The first working year of CRTC reveals a real demand in the field. About 30 trainings have been organized by CRTC during 1998. They have allowed about 150 people to be trained in characterization/production IC testing.

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection

Bulk Built-In Current Sensors (BBICSs) are able to detect anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. This paper presents a new strategy to design BBICSs with optimal transient-fault detection sensitivity while keeping low both area and power overheads. The approach allows increasing the detection sensitivity by setting an asymmetry in the flipping ability of the sensors latch. In addition, we introduce a mechanism to tune the delay of the bulk access transistors that improves even more the BBICS detection sensitivity. The proposed design strategy offers a good compromise between fault detection sensitivity and power consumption; moreover it makes feasible the use of several CMOS processes.

A remote access to engineering test facilities for the distant education of European microelectronics students

The European network for integrated circuit testing education described in this paper addresses the shortage of skill in mixed-signal production testing by encouraging students at pre- and post-doctoral levels to attend innovative training courses in the field, jointly supported by industry. The objective of the present educational experience is to strengthen given leading educational centers in Europe, in the critical field of mixed-signal testing, with the active support and guidance of industry. The project is an expansion of the successful French experience on engineering test education which allows any distant student to have a remote access to one-and one only-test resource center equipped with up-to-date/high-tech testers.

Power-Constrained Test Scheduling for SoCs Under a no session Scheme

This paper considers the scheduling problem of core tests in a system. Our objective is to minimize the total system test time while respecting system constraints in terms of power consumption and test resource sharing. A simple and effective scheduling heuristic is proposed based on a no sessions based scheme for better overall test time optimisation.

Testing system-in-package wirelessly

The paper shows a new concept for testing a system-in-package (SiP) using a wireless communication. Trends of the SiP technology put more economic and technical constraints onto the test, while the contactless test techniques represent an opportunity to overcome the inherent problems. In this paper, we introduce a new test concept based on a wireless communication, a specific test access mechanism (TAM), and an optimised architecture. Although this approach is dedicated to an intermediate test of SiP, we explore other potential applications of this technology

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis

ABSTRACT Hardware Trojan Horses (HTHs) are malicious and stealthy alterations of integrated circuits introduced at design or fabrication steps in order to modify a circuit’s intended behavior when deployed in the field. Due to HTHs’ stealth and diversity (intended alteration, implementation, triggering conditions), detecting and/or locating them is challenging. Several HTHs detection approaches have been proposed to address this problem. This paper focuses on so-called “side-channel analysis” methods, that is, methods that use power or delay measurements to detect potential HTHs. It reviews these methods and raises some considerations about the experiments made to evaluate them. Moreover, an original case study is presented in which we show that weak experiments may lead to misleading interpretations. Last, we evoke problems inherent to actual power and delay measurements.

On Countermeasures Against Fault Attacks on the Advanced Encryption Standard

This chapter presents redundancy-based error detection mechanisms deployed in devices implementing the Advanced Encryption Standard for preventing fault-based attacks. Different forms of redundancy are examined, highlighting strengths and weaknesses with regard to cost, global error detection capabilities, and ability to detect errors.