Bruno Rouzeyre

High-level synthesis for easy testability

This paper presents an attempt towards design quality improvement by incorporation of testability features during datapath high-level synthesis. This method is based on the use of hardware sharing possibilities to improve the testability of the circuit without a time consuming re-synthesis process. This is achieved by incorporating test constraints during register allocation and interconnect network generation. The main features of this method are: a test analysis at the behavioral level rather than at a structural one; the non limitation on the behavioral descriptions (loops, control constructs are supported); and the optimized test area overhead and CPU time compared to standard approach. The method was applied to several benchmarks resulting in easily testable designs for almost the same area costs as the original (without testability) designs.<<ETX>>

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS

Bulk Built-In Current Sensors (bbicss) were introduced to detect the anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. To date, the experimental testing of only one bbics architecture was reported in the scientific bibliography. It reports an unexpected weakness in its ability to monitor nmos transistors. Based on experimental measures, we propose an explanation of this weakness and also the use of triple-well cmos to offset it. Further, we introduce a new bbics architecture well suited for triple-well that offers high detection sensitivity and low area overhead.

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection

Bulk Built-In Current Sensors (BBICSs) are able to detect anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. This paper presents a new strategy to design BBICSs with optimal transient-fault detection sensitivity while keeping low both area and power overheads. The approach allows increasing the detection sensitivity by setting an asymmetry in the flipping ability of the sensors latch. In addition, we introduce a mechanism to tune the delay of the bulk access transistors that improves even more the BBICS detection sensitivity. The proposed design strategy offers a good compromise between fault detection sensitivity and power consumption; moreover it makes feasible the use of several CMOS processes.

Power-Constrained Test Scheduling for SoCs Under a no session Scheme

This paper considers the scheduling problem of core tests in a system. Our objective is to minimize the total system test time while respecting system constraints in terms of power consumption and test resource sharing. A simple and effective scheduling heuristic is proposed based on a no sessions based scheme for better overall test time optimisation.

Hardware/Software Co-Synthesis: Modelling and Synthesis of Interfaces Using Interpreted Petri Nets

When designing a system using software and hardware components, communication modelling and synthesis are key points, since, for instance, communications cost drive hardware/software partitioning. In this chapter we present a method for communication interface synthesis based on a multi-level modelling of communication. By using a specific synthesis tool for each description level, and libraries of protocols and synthesised modules, reuse possibilities are enhanced. Petri Nets are used to model protocol behaviours and evaluate communication capabilities, leading partitioning.

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis

ABSTRACT Hardware Trojan Horses (HTHs) are malicious and stealthy alterations of integrated circuits introduced at design or fabrication steps in order to modify a circuit’s intended behavior when deployed in the field. Due to HTHs’ stealth and diversity (intended alteration, implementation, triggering conditions), detecting and/or locating them is challenging. Several HTHs detection approaches have been proposed to address this problem. This paper focuses on so-called “side-channel analysis” methods, that is, methods that use power or delay measurements to detect potential HTHs. It reviews these methods and raises some considerations about the experiments made to evaluate them. Moreover, an original case study is presented in which we show that weak experiments may lead to misleading interpretations. Last, we evoke problems inherent to actual power and delay measurements.

Scanning datapaths: a fast and effective partial scan selection technique

Partial scan DFT is a commonly used technique for improving testability of sequential circuits while maintaining overhead as low as possible. In this context, the selection of the partial scan chain is usually performed at gate-level. In this paper, we present a method for quickly selecting the partial Scan Chain (SC) in datapath-like circuits. The so-obtained SC is such that the number of scan FFs is optimized and such that the achievable fault coverage is the same than with full scan approach.

Improving Testability of Non-Scan Designs during BehavioralSynthesis

We present a behavioral synthesis method aimed at generating testabledatapaths. A non-scan testing strategy is targeted. Given performanceand area constraints, the system is aimed at seeking among potentialdesign alternatives the one presenting the least testabilityproblems. The backbone of this methodology is a testability analysismethod that works at different abstraction levels of the designdescription—from strictly behavioral domain to purely structuraldomain. Considering a partially mapped behavioral specification, thetestability analysis identifies the testability problems of thefuture structure. These problems are solved along the synthesisprocess, for example during the register allocation/binding task aspresented in this paper.

Validation of differential light emission analysis on FPGA

Failure analysis tools and methods can be used for security purposes as well as the security attack techniques can be used in failure analysis. In this paper, we describe the last results obtained concerning light emission techniques and their use to set up a side channel methodology. From a cryptanalyst standpoint, the light emission could be a potential source of leakage. When studying a specific cipher algorithm implemented in a device, by analysing this new kind of leakage it is possible to retrieve secret sensitive data. We made our analyses on an FPGA device, which makes the attack harder to perform than on a standard ASIC. Furthermore, the technique was validated on a device in 0.13µm technology, resulting in a more complex sample preparation from backside. We will show that, the leakage due to the light emitted during normal operation of a CMOS circuit, can be used to set up an attack based on the well-known DPA technique.

A simple and effective compression scheme for test pins reduction

We present a simple and effective method for test pin reduction. It must be noticed first that this method is particularly well adapted to the test of SoC since it only deals with test data and does not require any knowledge of the embedded cores. Secondly, it does not induce any delay penalty neither in the circuit itself nor during decompression.