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Dive into the research topics where Marijan Jurgo is active.

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Featured researches published by Marijan Jurgo.


Journal of Electrical Engineering-elektrotechnicky Casopis | 2016

Design of Gigahertz Tuning Range 5 GHz LC Digitally Controlled Oscillator in 0.18 μm CMOS

Marijan Jurgo; R. Navickas

Abstract In this paper design and simulation of a 4.3 - 5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 μm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Structure of frequency divider is based on extended-true-single-phase-clock flip-flops. Divider is made of eight divide-by-2 cells connected in daisy chain, thus division values from 2 to 256 are available. Wide tuning range and high division values allows using such DCO with frequency divider in multi-standart transceivers. Whole device is supplied from a single 1.8 V voltage source. At highest frequency proposed device draws 90 mA current including all buffers. Phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier. Designed dual DCO and frequency divider occupies about 0.4mm×0.5mm of chip space and whole chip, including pads, occupies 1.5mm × 1.5mm area of silicon.


Mokslas - Lietuvos Ateitis | 2013

All Digital Phase-Locked Loop

Marijan Jurgo

The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33 to −82.17 dBc/Hz, with tres = 8.64–27.71 ps, TSVG = 143–333 ps, FREF = 20–60 MHz.


Elektronika Ir Elektrotechnika | 2013

Design of a Linear-in-dB Power Detector in 65nm CMOS Technology

Karolis Kiela; Marijan Jurgo; R. Navickas


Mokslas - Lietuvos Ateitis | 2016

Integrated Analogic Filter Tuning System Design

Karolis Kiela; Marijan Jurgo; Leonid Kladovščikov


Mokslas - Lietuvos Ateitis | 2018

2D Vernier žiedinio laikinio skaitmeninio keitiklio modelis / The model of 2D Vernier time to digital converter based on gated ring oscillators

Marijan Jurgo; R. Navickas


Przegląd Elektrotechniczny | 2017

Dual mode 4th order active-RC low-pass filter with tunable cut-off frequency from 3 MHz to 20 MHz in 65 nm CMOS

Karolis Kiela; Marijan Jurgo; R. Navickas


Mokslas - Lietuvos Ateitis | 2017

Increasing a Resolution of Time to Digital Converter

Marijan Jurgo; R. Navickas


Informacije Midem-journal of Microelectronics Electronic Components and Materials | 2017

Synthesizable 2D Vernier TDC based on gated ring oscillators

Marijan Jurgo; R. Navickas


2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE) | 2017

Comparison of TDC parameters in 65 nm and 0.13 μm CMOS

Marijan Jurgo; R. Navickas


Mokslas - Lietuvos Ateitis | 2016

Analysis of Frequency Synthesisers for Multistandart Wireless Transceiver

Marijan Jurgo; R. Navickas

Collaboration


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R. Navickas

Vilnius Gediminas Technical University

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Karolis Kiela

Vilnius Gediminas Technical University

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Jevgenij Charlamov

Vilnius Gediminas Technical University

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Leonid Kladovščikov

Vilnius Gediminas Technical University

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V. Barzdenas

Vilnius Gediminas Technical University

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Vytautas Mačaitis

Vilnius Gediminas Technical University

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