Mariko Shirazi

An Autotuning Digital Controller for DC–DC Power Converters Based on Online Frequency-Response Measurement

This paper describes a hardware-description-language-coded autotuning algorithm for digital PID-controlled DC-DC power converters based on online frequency-response measurement. The algorithm determines the PID controller parameters required to maximize the closed-loop bandwidth of the feedback control system while maintaining user-specified stability margins and integral-based no-limit-cycling criteria, as well as ensuring single-crossover-frequency operation and sufficiently high loop gain magnitude at low frequencies. Experimental results are provided for five different pulsewidth-modulated DC-DC converters, including a well-damped synchronous buck, a lightly damped synchronous buck with and without a poorly damped input filter, a boost operating in continuous-conduction mode, and a boost operating in discontinuous-conduction mode.

Autotuning Techniques for Digitally-Controlled Point-of-Load Converters with Wide Range of Capacitive Loads

This paper addresses auto-tuning of digital controllers for point-of-load (POL) switching converters with wide range of capacitive loads. Two auto-tuning methods are considered with particular attention given to robustness and feasibility. The first method is derived from the well known relay-feedback autotuning technique, where specific frequencies are excited to gain information on the power stage. In the second, system-identification based method, compensator parameters are computed based on on-line identification of the power stage frequency response. The tuning techniques proposed in this paper have been specifically developed to handle wide capacitance and ESR range, and important extensions of the basic algorithms are implemented in order to face practical issues such as limit cycling conditions, output voltage tolerance specification, closed-loop bandwidth maximization and phase margin constraints. Simulation and experimental results on a 12-to-1.5 V, 9 A, 200 kHz POL converter are provided to show the effectiveness and to compare the considered techniques.

Integration of Frequency Response Measurement Capabilities in Digital Controllers for DC–DC Converters

Recent work has shown the feasibility of integrating nonparametric frequency-domain system identification functionality into digital controllers for switched-mode pulse-width modulated (PWM) dc-dc power converters. The resulting discrete-time frequency response can be used for design, diagnostic, or self-tuning purposes. The success of these applications depends on the fidelity of the identified frequency responses and the degree to which the process is automated, as well as the costs, in terms of gate count, time duration of identification, and effect on output voltage, incurred to obtain these benefits. This paper demonstrates the feasibility of incorporating fully automated frequency response measurement capabilities in digital PWM controllers at relatively low additional cost. In particular, it is shown that relatively accurate and smooth frequency response data can be obtained using a Verilog-coded implementation with low tens of thousands of logic gates and about 10 kB of memory. The identification process can be accomplished in several hundred milliseconds and the output voltage can be kept within specified bounds during the entire process. Experimental results are provided for four different PWM dc-dc converters, including a synchronous buck with two different filter capacitors, a boost operating in continuous conduction mode (CCM), and a boost operating in discontinuous conduction mode (DCM).

Online Health Monitoring in Digitally Controlled Power Converters

Spacecraft power systems and other mission- critical applications require robust power delivery systems. This paper focuses on two aspects of power converter health monitoring: detecting and analyzing loss-related and frequency response-related changes. Two hardware-efficient algorithms are discussed that can be implemented without any additional sensing points other than those required for operation of the converter and with minimal additional digital hardware. It is shown that available converter operating information can be processed to detect a significant (e.g. 2x) change in the power MOSFET RON- In addition, a system identification-based approach with an additional digital pre-fllter is used to extract an accurate and useful frequency response of the converter despite large quantization noise caused by a low-resolution A/D converter. It is shown that this information can be used to accurately monitor the stability margins of the converter. The techniques are verified experimentally on a 90 W 50 V-15 V forward converter with FPGA control.

Electronic Ballast Control IC With Digital Phase Control and Lamp Current Regulation

A digital control architecture is presented for electronic ballasts that provides a phase sweep for reliable, soft lamp ignition and a smooth transition to lamp current regulation mode. The controller is based on an inner phase loop for fast regulation of the resonant tank operating point and an outer current loop for lamp current regulation. The inner loop operates on a simple digital control law that computes the required gate timing relative to the inductor current positive zero crossing. Phase control provides reliable drive of the resonant converter in the presence of large dynamic changes in the load impedance during lamp ignition and warm up and natural tracking of component variations with temperature and time. The primarily digital approach provides programmability for broad application, insensitivity to process and temperature variations, realization in low cost CMOS processes and few external components. Experimental results are presented for an integrated ballast controller fabricated in a 0.8 mum CMOS process used in a 400 W, 150 kHz HID electronic ballast.

Minimum Phase Response in Digitally Controlled Boost and Flyback Converters

This paper addresses modeling and control issues related to practical high-frequency digital PWM control of constant-frequency boost, buck-boost and flyback converters. Discrete-time models, including the effects of A/D sampling and delays in the digital control loop, are derived for two cases: output voltage A/D sampling during transistor off time in combination with trailing-edge (TE) DPWM, and A/D sampling during transistor on time in combination with leading-edge (LE) DPWM. We show that off-time sampling with TE-DPWM, which is a common approach in digital controller realizations, can result in desirable minimum-phase responses, thus simplifying compensator design in wide bandwidth closed-loop voltage regulators based on boost or flyback converters. The results are verified by simulation and experimental results on a boost converter prototype.

Fully integrated ballast controller with digital phase control

An integrated ballast controller fabricated in a 0.8 mum CMOS process is presented that includes digital phase control, current regulation and soft-start ignition. The primarily digital approach provides programmability for broad application, insensitivity to process and temperature variations, and few external components. Experimental results are provided for a 400 W HID electronic ballast

Implementation and validation of advanced unintentional islanding testing using power hardware-in-the-loop (PHIL) simulation

Unprecedented investment in new renewable power (especially solar photovoltaic) capacity is occurring. As this new generation capacity is interconnected with the electric power system (EPS), it is critical that their grid interconnection systems have proper controls in place so that they react appropriately in case of an unintentional islanding event. Advanced controls and methods for unintentional islanding protection that go beyond existing standards, such as UL 1741 and IEEE Std 1547, are often required as more complex high penetration photovoltaic installations occur. This paper describes the implementation, experimental results, and validation of a power hardware-in-the-loop (PHIL)-based platform that allows for the rapid evaluation of advanced anti-islanding and other controls in complex scenarios. The PHIL-based approach presented allows for accurate, real-time simulation of complex scenarios by connecting a device under test to a software-based model of a local EPS. This approach was validated by conducting an unintentional islanding test of a photovoltaic inverter, as described in IEEE 1547.1, using both PHIL and discrete hardware-based test configurations. The comparison of the results of these two experiments demonstrates that this novel PHIL-based test platform accurately emulates traditional unintentional islanding tests. The advantage of PHIL-based testing over discrete hardware-only testing is demonstrated by completing an IEEE 1547.1 unintentional islanding test using a very precisely tuned resonant circuit that is difficult to realize with discrete hardware using PHIL.

Rapid Active Power Control of Photovoltaic Systems for Grid Frequency Support

As deployment of power electronic coupled generation such as photovoltaic (PV) systems increases, grid operators have shown increasing interest in calling on inverter-coupled generation to help mitigate frequency contingency events by rapidly surging active power into the grid. When responding to contingency events, the faster the active power is provided, the more effective it may be for arresting the frequency event. This paper proposes a predictive PV inverter control method for very fast and accurate control of active power. This rapid active power control (RAPC) method will increase the effectiveness of various higher-level controls designed to mitigate grid frequency contingency events, including fast power-frequency droop, inertia emulation, and fast frequency response, without the need for energy storage. The RAPC method, coupled with a maximum power point estimation method, is implemented in a prototype PV inverter connected to a PV array. The prototype inverter’s response to various frequency events is experimentally confirmed to be fast (beginning within 2 line cycles and completing within 4.5 line cycles of a severe test event) and accurate (below 2% steady-state error).

Advanced photovoltaic inverter control development and validation in a controller-hardware-in-the-loop test bed

Penetration levels of solar photovoltaic (PV) generation on the electric grid have increased in recent years. In the past, most PV installations have not included grid-support functionalities. But today, standards such as the upcoming revisions to IEEE 1547 recommend grid support and anti-islanding functions-including volt-var, frequency-watt, volt-watt, frequency/voltage ride-through, and other inverter functions. These functions allow for the standardized interconnection of distributed energy resources into the grid. This paper develops and tests low-level inverter current control and high-level grid support functions. The controller was developed to integrate advanced inverter functions in a systematic approach, thus avoiding conflict among the different control objectives. The algorithms were then programmed on an off-the-shelf, embedded controller with a dual-core computer processing unit and field-programmable gate array (FPGA). This programmed controller was tested using a controller-hardware-in-the-loop (CHIL) test bed setup using an FPGA-based real-time simulator. The CHIL was run at a time step of 500 ns to accommodate the 20-kHz switching frequency of the developed controller. The details of the advanced control function and CHIL test bed provided here will aide future researchers when designing, implementing, and testing advanced functions of PV inverters.