Jeffrey Morroni

Comparison of a Buck Converter and a Series Capacitor Buck Converter for High-Frequency, High-Conversion-Ratio Voltage Regulators

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3-30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%.

Dual-frequency SIMO power converters for low-power on-chip power grids in SoCs

This paper introduces the Dual-Frequency Single-Inductor Multiple-Output (DF-SIMO) power converter topology as a cost-effective and power-efficient method for implementing a large number of on-chip power supplies (i.e. on-chip power grids) in nanometer CMOS System-on-Chip (SoCs). The proposed topology decouples the rate of energy conversion at the input of the converter from the rate of energy distribution to the outputs, and thus, output bandwidth and dynamic behavior become no longer limited by the switching frequency at the input side. Low switching frequency at the input side can be used to preserve high power conversion efficiency, while high switching frequency for energy distribution at the output side can be used to reduce the output capacitors to integrate-able levels where they can be implemented on-chip. This limits off-chip components to a single inductor and reduces the package pin count, which results into a lower overall cost per power supply. Dynamic performance is also improved due to the high frequency energy distribution. A 5-output DF-SIMO buck converter design in 45nm CMOS is introduced as an application to the proposed concept.

A series-capacitor tapped buck (SC-TaB) converter for regulated high voltage conversion ratio DC-DC applications

This paper explores a Series-Capacitor Tapped Buck (SC-TaB) converter for regulated high voltage conversion ratio dc-dc applications targeting high efficiency and high power density. By adding one series capacitor and one auxiliary switch to the conventional tapped inductor buck converter, the proposed converter features many advantages including: (1) full soft switching; (2) reduced parasitic ringing; (3) capacitive energy buffering; (4) extended duty ratio; (5) reduced switch stress and (6) high efficiency over wide operating ranges. Experimental results of a 48V/5V, 750kHz, 100W, two-phase-interleaved dc-dc converter shows 91% peak efficiency, and above 88% efficiency over 38-58V input voltage range and 25-75W power range.

Quasi-square wave converters-modeling and performance benefits of GaN over Silicon

This paper presents an accurate loss model of a Quasi-Square Wave (QSW) buck converter and analyzes the efficiency benefits of GaN FETs over Silicon super-junction FETs. A design methodology and optimization strategy is presented while accounting for the FET Figures-of-Merit (FoM). The model uses computational techniques to account for non-linear device capacitances and precisely predicts the FET on times, resonant intervals and switching frequency required for ZVS operation. Analyses show the FET RDS,ON-QOss FoM has the maximum impact in the efficiency affecting both FET and inductor losses and a FoM dependent optimal RDS,ON exists for which the FET conduction losses balance the inductor losses. The loss model is validated by two QSW buck converters designs operating at 36W using GaN and Silicon FETs, each optimized to maximize their end-to-end efficiencies.