Mario Garcia Valderas

SET Emulation Considering Electrical Masking Effects

A new approach is proposed for evaluating circuit robustness against Single Event Transients (SETs) through FPGA emulation. A voltage-time quantization model allows capturing circuit delays in the FPGA, including electrical masking effects. Experimental results demonstrate this approach improves SET fault injection rate by three orders of magnitude with respect to logic simulation and provides an accuracy close to analog simulation.

Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.

Analysis of SET Effects in a PIC Microprocessor for Selective Hardening

In this work we propose a method to evaluate the criticality of the components of a circuit with respect to Single Event Transient (SET) effects. Emulation-based fault injection is used to determine the error rate for each individual gate. The method also identifies the optimal set of flip-flops to be hardened using time redundancy techniques. The results enable the selective application of SET mitigation techniques to satisfy soft error rate requirements with reduced overheads. A PIC18 microprocessor with three different workloads has been used as a case study, and results show that just hardening 25% of gates is enough to achieve more than 99% mitigation of SET effects.

Power Consumption Reduction Through Dynamic Reconfiguration

Dynamic reconfiguration optimizes the use of hardware resources, and therefore may produce important reductions in power consumption. However, in a reconfigurable system the power consumption produced by the reconfiguration process itself must be taken into account. In this work the reconfiguration power consumption is characterized for a SRAM FPGA. In particular, we show that reconfiguration must be made at the highest frequency available in order to reduce power consumption. The results obtained allow to quantify the tradeoff between the energy saved by the use of dynamic reconfiguration and the energy wasted by the reconfiguration process. In this way, the power consumption reduction that can be obtained with the use of dynamic reconfiguration can be estimated.

Two Complementary Approaches for Studying the Effects of SEUs on Digital Processors

This paper describes two different but complementary approaches that can be used to perform SEU-like fault injection sessions in order to predict error rates of digital processors. The code emulated upset (CEU) approach allows fault injection in processor memories (caches and register files), while the FPGA autonomous emulation approach allows fault injection in processor flip-flops. Results obtained for a case studied, the LEON processor, illustrate the complementary aspects of proposed strategies.

Advanced Simulation and Emulation Techniques for Fault Injection

The environment can produce transient faults in digital circuits, especially nowadays with the new technology development. Fault injection has been widely used to evaluate the hardness degree of circuits in which fault tolerance is a requirement, like aerospace or automotive applications. The magnitude of the fault effects evaluation problem is computationally unaffordable, if an exhaustive test must be performed on a circuit. Several solutions have been proposed to improve the performance of the process. Simulation based fault injection offers slower execution speed, but a great flexibility in the fault injection campaign. Emulation based solution are much faster, but not so flexible. In this paper, the fault injection problem is analysed from a performance point of view, and some optimized solutions are proposed.

Extensive SEU Impact Analysis of a PIC Microprocessor for Selective Hardening

In order to increase the robustness of a circuit against SEUs, fault injection is commonly used to locate weak areas. autonomous emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to a PIC18 microprocessor, while executing three different workloads. A 80 million fault campaign has been performed, and results show that a failure rate lower than 1% can be obtained by hardening a 24% of the circuit flip-flops, for the given applications.

Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion

In this paper, we present a technique and a tool to debug microprocessor systems implemented in FPGAs. We propose a method based on debug logic insertion and a set of debug modules to provide soft core microprocessors with In-Circuit Emulation capabilities.

A recovery mechanism for SET protection using standard-cells

The traditional way for protecting a digital circuit against Single Event Transients (SET) implies the triplication and voting of the combinational logic in the circuit. This approach uses a high area overhead. Other approaches imply the design of specific SET hardened cells, but they are rarely available. In this paper a technique for detecting and correcting radiation-induced soft errors in combinational logic is presented. This technique offers a good protection against SET effects, with a reasonable area overhead compared to those of TMR approaches, and with little impact in the circuit performance. In addition, the proposed method uses standard cells from ASIC libraries and can be easily integrated in common ASIC design flows and tools. Results show that with this proposal, SET effects can be reduced between 90% to 100%, depending on the SET pulse width.

Briefing power/reliability optimization in embedded software design

We propose an approach1 to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints are verified at runtime by the processor against compilation-time pre-computed values every time the processor reaches these points. Experiments with a PIC18 microcontroller have been carried out to demonstrate the benefits from using the proposed approach.