Mario Kittler

On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs

Abstract The drain currents of nanometer double-gate MOSFETs with gate lengths in the range from 100 to 5 nm are calculated using a hierarchy of simulation approaches. By comparing Monte Carlo (MC), drift-diffusion (DD), and hydrodynamic (HD) simulation results the suitability of the DD and HD models for the investigation of the on- and subthreshold currents of nano-scaled MOSFETs is tested. Modifications of the velocity-field characteristics in the DD simulations are suggested to improve the accuracy of the DD model.

Vertical design of cubic GaN-based high electron mobility transistors

Cubic (zinc blende) AlGaN/GaN heterostructures for application in GaN-based high electron mobility transistors are investigated theoretically. The formation of 2DEGs (two-dimensional electron gas) in cubic AlGaN/GaN structures is studied, carrier distributions and threshold voltages are calculated, and design issues are investigated. For the calculations, a Schrodinger-Poisson solver and a simple analytical model developed in the present work are used. It is shown that due to the barrier doping needed for the formation of a pronounced 2DEG in cubic structures, undesirable saturation effects of the 2DEG density may occur. Options to avoid 2DEG saturation and to realize cubic normally-off HEMTs are elaborated. The behavior of cubic AlGaN/GaN structures is compared to that of their hexagonal counterparts.

2H-AlGaN/GaN HEMTs on 3C-SiC(111)/Si(111) Substrates

We present the realization of high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures grown on silicon substrates using a SiC transition layer. The growth of AlGaN/GaN heterostructures on Si (111) was performed using metalorganic chemical vapour deposition (MOCVD). The (111) SiC transition layer was realized by low pressure CVD and prevented Ga-induced meltback etching and Si-outdiffusion in the subsequent MOCVD growth. The two-dimensional electron gas (2DEG) formed at the AlGaN/GaN interface showed an electron sheet density of 1.5x1013 cm-3 and a mobility of 870 cm²/Vs proving the high structural quality of the heterostructure. Device processing was done using electron beam lithography. DC and RF characteristics were analysed and showed a peak cut-off frequency as high as 6 GHz for a 1.2 µm gate HEMT.

Model of Coupled Defect Level Recombination with Participation of Multiphonons

We present a new model of two coupled defect-level recombination. Calculation of the generation and recombination rates is based on the so-called exchange times. These allow calculating the occupation probability of the trapping centres and subsequently the generation-recombination rates of free charge carriers appearing in the continuity equations. Each of these two coupled defect levels has its specific trap density, position in the forbidden band and capture cross-section obtained from DLTS measurements.

Simulation of Random Telegraph Noise in Nanometer nMOSFET Induced by Interface and Oxide Trapped Charge

In this work, the influence of a single positive elementary charge trapped either in the oxide or at the oxide-semiconductor interface on Random Telegraph Noise (RTN) has been investigated and the relative RTN amplitude ΔI D ∕ I D in nanometer MOSFET was simulated. Since our investigations were focused on the RTN amplitude, we considered only the steady-state and did not investigate the dynamics of charging/discharging the trap.

Vertical design of InN field effect transistors

The vertical design of indium nitride field effect transistors is investigated by numerical simulation. To this end, the Schrödinger equations for electrons and holes and Poissons equation are solved self-consistently. It is shown that in several layer sequences simultaneously two-dimensional electron and hole gases are formed in the InN channel. It is demonstrated that because of the high unintentional n-type doping only thin InN layers are useful for proper transistor operation. Strain in the InN layer leads to the formation of parasitic hole channels which can dramatically deteriorate transistor characteristics. Finally it is shown that thin relaxed InN channels on GaN or AlInN buffers are a viable option for InN transistors.