Ralf Granzner

On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs

Abstract The drain currents of nanometer double-gate MOSFETs with gate lengths in the range from 100 to 5 nm are calculated using a hierarchy of simulation approaches. By comparing Monte Carlo (MC), drift-diffusion (DD), and hydrodynamic (HD) simulation results the suitability of the DD and HD models for the investigation of the on- and subthreshold currents of nano-scaled MOSFETs is tested. Modifications of the velocity-field characteristics in the DD simulations are suggested to improve the accuracy of the DD model.

An Analytical Model for the Threshold Voltage Shift Caused by Two-Dimensional Quantum Confinement in Undoped Multiple-Gate MOSFETs

An analytical model describing the effects of 2-D quantum-mechanical carrier confinement on the threshold voltage Vth of multiple-gate MOSFETs with rectangular cross section is developed. The model is verified by a comparison with self-consistent solutions of 1-D and 2-D Schroumldinger and Poisson equations. It is shown that: 1) the model results asymptotically approach the case of 1-D confinement in single-gate silicon-on-insulator or double-gate MOSFETs if one body dimension becomes larger than 20 nm and 2) the effect of 2-D confinement is remarkably stronger than a simple combination of two 1-D quantization effects.

Influence of channel width on n - and p -type nano-wire-MOSFETs on silicon on insulator substrate

The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate stracture on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 nm. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices.

Side-gate graphene field-effect transistors with high transconductance

We have fabricated epitaxial side-gate graphene field-effect transistors (FETs) with high transconductance. A side-gate graphene FET with 55 × 60 nm2 active channel dimensions and a lateral gate-channel separation of 95 nm showing a high transconductance of 590 mS/mm is presented. An estimation of the electrostatic gate-channel capacitance of epitaxial side-gate graphene FETs shows that it is in the same order as the electrostatic gate capacitance of common top-gate graphene MOSFETs justifying the high transconductances of our devices. The results of the present paper demonstrate the potential of the side-gate architecture for graphene transistors.

Quantum Effects on the Gate Capacitance of Trigate SOI MOSFETs

Scaling effects on the gate capacitance of trigate MOS field-effect transistors are studied by means of analytical models and numerical self-consistent solutions of the 2-D Schrödinger and Poisson equations. Special attention is paid to the quantum capacitance, which is related to the density of states. We show that, although the quantum capacitance strongly decreases when the channel dimensions are scaled, the gate capacitance is not reduced relative to the oxide capacitance in trigate MOS structures. This is due to the fact that both the oxide capacitance and the quantum capacitance scale with the channel cross section. From Schrödinger-Poisson simulations, we actually observe a relative increase in the gate capacitance when the silicon cross section is scaled below 7 nm × 7 nm, whereas the opposite trend is obtained from classical calculations. We relate this mainly to the differences between quantum-mechanical and classical electron distributions in real space. Quantization effects on the quantum capacitance are found to have less effect on the gate capacitance except for very small silicon cross sections in the order of 2 nm × 2 nm.

Theoretical Investigation of Trigate AlGaN/GaN HEMTs

The operation of AlGaN/GaN trigate high-electron mobility transistor (HEMT) structures is investigated by numerical simulations. It is shown that the threshold voltage of such structures strongly depends on the width of the AlGaN/GaN bodies and that solely by decreasing the body width a transition from normally-on to normally-off operation can be achieved. Furthermore, the impact of uncertain device and/or material parameters such as strain relaxation, Schottky barrier heights, and dielectric constants on the threshold voltage is studied as well as the influence of the AlGaN barrier design (Al content, thickness). The results of this paper show that the trigate concept is a viable option to realize normally-off AlGaN/GaN HEMTs.

Nonpolar cubic AlGaN/GaN heterojunction field-effect transistor on Ar+ implanted 3C-SiC (001)

A heterojunction field-effect transistor (HFET) was fabricated of nonpolar cubic AlGaN/GaN grown on Ar+ implanted 3C–SiC (001) by molecular beam epitaxy. The device shows a clear field effect at positive bias voltages with Vth=0.6 V. The HFET output characteristics were calculated using ATLAS simulation program. The electron channel at the cubic AlGaN/GaN interface was detected by room temperature capacitance-voltage measurements.

The coexistence of two-dimensional electron and hole gases in GaN-based heterostructures

The formation of two-dimensional carrier gases in gated GaN/AlGaN/GaN heterostructures is investigated theoretically. It is shown that under certain conditions a two-dimensional hole gas at the upper GaN/AlGaN interface can be formed in addition to the two-dimensional electron gas at the lower AlGaN/GaN interface. For the calculations, a Schrodinger-Poisson solver and a simple analytical model developed in the present work are used. Conditions for the formation of a two-dimensional hole gas are elaborated. It is shown that once a two-dimensional hole gas is created, it shields the coexisting two-dimensional electron gas which will result in a diminishing effect of the gate voltage on the two-dimensional electron gas.

Empirical Model for the Effective Electron Mobility in Silicon Nanowires

An empirical model for the effective electron mobility in silicon nanowires (SiNWs) is presented. The model is based on published mobility data from numerical simulations of electron transport in SiNWs with different cross sections. Both phonon scattering and surface roughness scattering as well as the impact of the effective vertical field are considered. A comparison with a variety of experimental mobility data from the literature shows that the model can be treated as a reference for benchmarking different NW technologies. The effective field dependence is modeled by a simple expression making our mobility model very efficient for the use in numerical device simulators or in analytical MOSFET models.

High-Current Submicrometer Tri-Gate GaN High-Electron Mobility Transistors With Binary and Quaternary Barriers

Through implementation of the 3-D tri-gate topology, GaN-based high-electron mobility transistors (HEMTs) have been fabricated and high-frequency performances as well as the short-channel effects are investigated. The designed tri-gate transistors are highly-scaled having 100 nm of gate length, which introduces the condition of a short channel. It is demonstrated that higher sub-threshold slopes, reduced drain-induced barrier lowering and better overall off-state performances have been achieved by the nano-channel tri-gate HEMTs with an AlGaN barrier. A lattice-matched InAlGaN barrier with the help of the fin-shaped nano-channels provide improved gate control, increasing current densities, and transconductance gm. In a direct comparison, very high drain current densities (~3.8 A/mm) and gm (~550 mS/mm) have further been obtained by employing a pure AlN barrier.