Mario Micciche

A 90nm Embedded Page Flash for EEPROM Replacement in System On Chip

Today, the most widely diffused and popular non volatile memory solutions for system on chip (SOC) are Flash and EEPROM. EEPROM is especially useful for applications not requiring a large amount of memory and strongly demanding for a very high number of W/E cycles in conjunction with capability to erase small amount of memory (word size) in a short time (few ms). On the other hand the Flash solution is more attractive for applications with higher amount of memory, not requiring erasing at word level. Focusing on the field of SIM Market (Smartcard for Telecom application), the trend today is to reduce cost while keeping almost the same amount of NVM memory, with the ROM size slightly increasing due to the introduction of new software features. This caused a price pressure and forced major SIM Suppliers in the reduction of NVM cell size. In this scenario EEPROM has been scaled down to the ultimate limit for 2T architecture, showing an evident difficulty in a further scaling down perspective. At the same time, the feature of ROM personalization is also a cost, and ROM replacement with NMV would be more than welcome. This paper illustrates a solution addressing both problems, with the adoption of a scalable Flash cell and a proper Memory Architecture integrated in 90 nm CMOS technology, first in the world for SIM applications.