Mark B. Josephs

CMOS design of the tree arbiter element

An asynchronous arbiter dynamically allocates a resource in response to requests from processes. Glitch-free operation when two requests arrive concurrently is possible in MOS technologies. Multiway arbitration using a request-grant-release-acknowledge protocol can be achieved by connecting together two-way arbiters (mutual exclusion and tree arbiter elements). We have devised a fast and compact design for the tree arbiter element which offers eager forward-propagation of requests. It compares favorably with a well-known design in which request propagation must wait for arbitration to complete. Our analysis and simulations also suggest that no performance improvement will be obtained by incorporating eager acknowledgment of releases. All of the designs considered in this paper are speed-independent, a formal property of a network of elements which can be taken as a positive indication of their robustness.

Modelling and verification of delay-insensitive circuits using CCS and the concurrency workbench

The modelling of delay-insensitive asynchronous circuits in the process calculus CCS is addressed. MUST-testing (rather than bisimulation) is found to support verification both of file property of delay-insensitivity and of design by stepwise refinement. Automated verification is possible with a well-known tool, the Edinburgh Concurrency Workbench.

A Programming Approach to the Design of Asynchronous Logic Blocks

Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchronous logic block is to interact with its environment. Using the tool di2pn, such a specification can be automatically translated into a Petri net. Using the tool petrify, the net can be automatically validated (for freedom from deadlock and interference, and for implementability as a speed-independent circuit) and asynchronous logic can be automatically synthesised.

Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra

Two recent developments in asynchronous circuit design are explored by means of a case study (polynomial division) in digital signal processing. The first development is a new formal method, the handshake algebra of M.B. Josephs, J.T. Udding and J.T. Yantchev (1993), that is suitable for specifying, deriving, and verifying circuits that follow a handshaking protocol. The second development is an architecture, counterflow pipelines, that R.F. Sproull (1994) has recently suggested, which is attractive to implement asynchronously.

An analysis of determinacy using a trace-theoretic model of asynchronous circuits

Receptive process theory provides a semantic model for reasoning about input/output-systems in general, and about the switching behaviour of asynchronous circuits in particular. As in the failures/divergences model of Hoares CSP, nondeterministic behaviour, as might result from the use of arbiters and synchronizers, can be modelled. A new result is the identification of the class of deterministic receptive processes, which is closed under composition. The defining characteristic of the class is that the behaviour of its members can be adequately described using a traces/divergences model. The closure of the class is proved with respect to a binary, parallel composition operator which allows inputs to be forked isochronically to both components and which conceals those outputs of either component that are inputs to the other component. This result contrasts with CSP, in which determinacy is not preserved when events are concealed.

Delay-insensitive interface specification and synthesis

Delay insensitive interfacing was first demonstrated on the macromodules project in the 1960s, but globally synchronous (clocked) schemes have so far dominated the VLSI era. In deep sub-micron technologies, problems of clock skew, including excessive size and power consumption of black buffers, and heterogeneity of systems on a chip are rekindling an interest in global asynchrony. DI-Algebra is presented here as a language for the specification of modules with delay-insensitive interfaces. Such modules can be implemented either in synchronous or in asynchronous logic. A design flow is also illustrated in which specifications are automatically translated into Petri nets, validated and synthesised into asynchronous logic.

Specifying distributed CICS in Z: Accessing local and remote resources

The CICS/ESA Intercommunication Guide is a source of information about distributed CICS systems. Among other things, it describes how an application program running on one system can issue a command that will be shipped to a remote system. A resource manager located at the remote system will execute the command and ship back a response.This paper presents a formal specification of the above interaction between application programs and resource managers. Some familiarity with the Z specification language is assumed. The structure of the specification illustrates how it is possible to address separately, and later combine, different aspects of a complex system, including its distributed nature.

A formal description of the OMG's Core Object Model and the meaning of compatible extension

Abstract The Object Management Groups Core Object Model provides a standard type structure that must be supported by compliant object-oriented systems (such as IBMs SOM Object Request Broker) and languages (such as C ++ ). The standard is expressed in prose and punctuated by several small examples. The standard also attempts to convey the idea of compatible extensions to the model. The objective of the work reported here was to understand and to communicate the essence of the above standard by use of a formal description technique, the Z notation. In so doing, the meaning of compatibility was clarified. These efforts have been well-received by authors of the original standard.

Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis

Synthesis of asynchronous logic using the tool Petrify requires a state graph with a complete state coding. It is common for specifications to exhibit concurrent outputs, but Petrify is sometimes unable to resolve the state coding conflicts that arise as a result, and hence cannot synthesise a circuit. A pair of decomposition heuristics (expressed in the language of Delay-Insensitive Sequential Processes) are given that helps one to obtain a synthesisable specification. The second heuristic has been successfully applied to a set of nine benchmarks to obtain significant reductions both in area and in synthesis time, compared with synthesis performed on the original specifications.

Gate-level modelling and verification of asynchronous circuits using CSPM and FDR

FDR (failures-divergences refinement) is a tool for verifying properties of processes expressed in a machine-readable dialect of CSP (CSPM). This paper shows how to model asynchronous logic blocks as processes in CSPM and how to verify them using FDR: processes abstract away from the speed of the blocks; multi-way synchronization facilitates the modelling of isochronic forks; receptiveness is formalised as an assertion for FDR to check; process trans formations allow one to model transmission lines and handshaking ports. A process parameterised by a Boolean function suffices to model any complex gate; another such process models N-way mutual exclusion. The approach is illustrated on a variety of asynchronous circuits drawn from the literature.