Mark Barnell

Anatomy of Ag/Hafnia‐Based Selectors with 1010 Nonlinearity

A novel Ag/oxide-based threshold switching device with attractive features including ≈1010 nonlinearity is developed. High-resolution transmission electron microscopic analysis of the nanoscale crosspoint device suggests that elongation of an Ag nanoparticle under voltage bias followed by spontaneous reformation of a more spherical shape after power off is responsible for the observed threshold switching.

RENO: a high-efficient reconfigurable neuromorphic computing accelerator design

Neuromorphic computing is recently gaining significant attention as a promising candidate to conquer the well-known von Neumann bottleneck. In this work, we propose RENO - a efficient reconfigurable neuromorphic computing accelerator. RENO leverages the extremely efficient mixed-signal computation capability of memristor-based crossbar (MBC) arrays to speedup the executions of artificial neural networks (ANNs). The hierarchically arranged MBC arrays can be configured to a variety of ANN topologies through a mixed-signal interconnection network (M-Net). Simulation results on seven ANN applications show that compared to the baseline general-purpose processor, RENO can achieve on average 178.4× (27.06×) performance speedup and 184.2× (25.23×) energy savings in high-efficient multilayer perception (high-accurate auto-associative memory) implementation. Moreover, in the comparison to a pure digital neural processing unit (D-NPU) and a design with MBC arrays co-operating through a digital interconnection network, RENO still achieves the fastest execution time and the lowest energy consumption with similar computation accuracy.

Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems

Neuromorphic computing system (NCS) is a promising architecture to combat the well-known memory bottleneck in Von Neumann architecture. The recent breakthrough on memristor devices made an important step toward realizing a low-power, small-footprint NCS on-a-chip. However, the currently low manufacturing reliability of nano-devices and the voltage IR-drop along metal wires and memristors arrays severely limits the scale of memristor crossbar based NCS and hinders the design scalability. In this work, we propose a novel system reduction scheme that significantly lowers the required dimension of the memristor crossbars in NCS while maintaining high computing accuracy. An IR-drop compensation technique is also proposed to overcome the adverse impacts of the wire resistance and the sneak-path problem in large memristor crossbar designs. Our simulation results show that the proposed techniques can improve computing accuracy by 27.0% and 38.7% less circuit area compared to the original NCS design.

Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO2 Memristor

Memristive devices are promising candidates for the next generation non-volatile memory and neuromorphic computing. It has been widely accepted that the motion of oxygen anions leads to the resistance changes for valence-change-memory (VCM) type of materials. Only very recently it was speculated that metal cations could also play an important role, but no direct physical characterizations have been reported yet. Here we report a Ta/HfO2/Pt memristor with fast switching speed, record high endurance (120 billion cycles) and reliable retention. We programmed the device to 24 discrete resistance levels, and also demonstrated over a million (220) epochs of potentiation and depression, suggesting that our devices can be used for both multi-level non-volatile memory and neuromorphic computing applications. More importantly, we directly observed a sub-10 nm Ta-rich and O-deficient conduction channel within the HfO2 layer that is responsible for the switching. This work deepens our understanding of the resistance switching mechanism behind oxide-based memristive devices and paves the way for further device performance optimization for a broad spectrum of applications.

A novel true random number generator based on a stochastic diffusive memristor

The intrinsic variability of switching behavior in memristors has been a major obstacle to their adoption as the next generation of universal memory. On the other hand, this natural stochasticity can be valuable for hardware security applications. Here we propose and demonstrate a novel true random number generator utilizing the stochastic delay time of threshold switching in a Ag:SiO2 diffusive memristor, which exhibits evident advantages in scalability, circuit complexity, and power consumption. The random bits generated by the diffusive memristor true random number generator pass all 15 NIST randomness tests without any post-processing, a first for memristive-switching true random number generators. Based on nanoparticle dynamic simulation and analytical estimates, we attribute the stochasticity in delay time to the probabilistic process by which Ag particles detach from a Ag reservoir. This work paves the way for memristors in hardware security applications for the era of the Internet of Things.Memristors can switch between high and low electrical-resistance states, but the switching behaviour can be unpredictable. Here, the authors harness this unpredictability to develop a memristor-based true random number generator that uses the stochastic delay time of threshold switching

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2 /Si memristors

Memristors are promising building blocks for the next-generation memory and neuromorphic computing systems. Most memristors use materials that are incompatible with the silicon dominant complementary metal-oxide-semiconductor technology, and require external selectors in order for large memristor arrays to function properly. Here we demonstrate a fully foundry-compatible, all-silicon-based and self-rectifying memristor that negates the need for external selectors in large arrays. With a p-Si/SiO2/n-Si structure, our memristor exhibits repeatable unipolar resistance switching behaviour (105 rectifying ratio, 104 ON/OFF) and excellent retention at 300 °C. We further build three-dimensinal crossbar arrays (up to five layers of 100 nm memristors) using fluid-supported silicon membranes, and experimentally confirm the successful suppression of both intra- and inter-layer sneak path currents through the built-in diodes. The current work opens up opportunities for low-cost mass production of three-dimensional memristor arrays on large silicon and flexible substrates without increasing circuit complexity.

A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy

Matrix-vector multiplication, as a key computing operation, has been largely adopted in applications and hence greatly affects the execution efficiency. A common technique to enhance the performance of matrix-vector multiplication is increasing execution parallelism, which results in higher design cost. In recent years, new devices and structures have been widely investigated as alternative solutions. Among them, memristor crossbar demonstrates a great potential for its intrinsic support of matrix-vector multiplication, high integration density, and built-in parallel execution. However, the computation accuracy and speed of such designs are limited and constrained by the features of crossbar array and peripheral circuitry. In this work, we propose a new memristor crossbar based computing engine design by leveraging a current sensing scheme. High operation parallelism and therefore fast computation can be achieved by simultaneously supplying analog voltages into a memristor crossbar and directly detecting weighted currents through current amplifiers. The performance and effectiveness of the proposed design were examined through the implementation of a neural network for pattern recognition based on MNIST database. Compared to a prior reported design, ours increases the recognition accuracy 8.1% (to 94.6%).

A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip

IBM TrueNorth chip uses digital spikes to perform neuromorphic computing and achieves ultrahigh execution parallelism and power efficiency. However, in TrueNorth chip, low quantization resolution of the synaptic weights and spikes significantly limits the inference (e.g., classification) accuracy of the deployed neural network model. Existing workaround, i.e., averaging the results over multiple copies instantiated in spatial and temporal domains, rapidly exhausts the hardware resources and slows down the computation. In this work, we propose a novel learning method on TrueNorth platform that constrains the random variance of each computation copy and reduces the number of needed copies. Compared to the existing learning method, our method can achieve up to 68.8% reduction of the required neuro-synaptic cores or 6.5× speedup, with even slightly improved inference accuracy.

A heterogeneous computing system with memristor-based neuromorphic accelerators

As technology scales, on-chip heterogeneous architecture emerges as a promising solution to combat the power wall of microprocessors. In this work, we propose a heterogeneous computing system with memristor-based neuromorphic computing accelerators (NCAs). In the proposed system, NCA is designed to speed up the artificial neural network (ANN) executions in many high-performance applications by leveraging the extremely efficient mixed-signal computation capability of nanoscale memristor-based crossbar (MBC) arrays. The hierarchical MBC arrays of the NCA can be flexibly configured to different ANN topologies through the help of an analog Network-on-Chip (A-NoC). A general approach which translates the target codes within a program to the corresponding NCA instructions is also developed to facilitate the utilization of the NCA. Our simulation results show that compared to the baseline general purpose processor, the proposed system can achieve on average 18.2X performance speedup and 20.1X energy reduction over nine representative applications. The computation accuracy degradation is constrained within an acceptable range (e.g., 11%), by considering the limited data precision, realistic device variations and analog signal fluctuations.

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators

Following technology scaling, on-chip heterogeneous architecture emerges as a promising solution to combat the power wall of microprocessors. This work presents Harmonica-a framework of heterogeneous computing system enhanced by memristor-based neuromorphic computing accelerators (NCAs). In Harmonica, a conventional pipeline is augmented with a NCA which is designed to speedup artificial neural network (ANN) relevant executions by leveraging the extremely efficient mixed-signal computation capability of nanoscale memristor-based crossbar (MBC) arrays. With the help of a mixed-signal interconnection network (M-Net), the hierarchically arranged MBC arrays can accelerate the computation of a variety of ANNs. Moreover, an inline calibration scheme is proposed to ensure the computation accuracy degradation incurred by the memristor resistance shifting within an acceptable range during NCA executions. Compared to general-purpose processor, Harmonica can achieve on average 27.06 × performance speedup and 25.23 × energy savings when the NCA is configured with auto-associative memory (AAM) implementation. If the NCA is configured with multilayer perception (MLP) implementation, the performance speedup and energy savings can be boosted to 178.41 × and 184.24 ×, respectively, with slightly degraded computation accuracy. Moreover, the performance and power efficiency of Harmonica are superior to the designs with either digital neural processing units (D-NPUs) or MBC arrays cooperating with a digital interconnection network. Compared to the baseline of general-purpose processor, the classification rate degradation of Harmonica in MLP or AAM is less than 8% or 4%, respectively.