Mark Brillhart

Reliability assessment of a high CTE CBGA for high availability systems

High availability network switches and routers employ high power dissipation ASICs that operate at near 100% utilization in a wide range of end-use environments. Ceramic ball grid array (CBGA) packages are typically employed to address these extreme thermal loading conditions. These ceramic packages exhibit a high coefficient of thermal expansion (CTE) differential when compared to the FR-4 printed circuit board. This large CTE mismatch results in a CBGA solder joint reliability that is significantly lower than that of a plastic ball grid array (PBGA) package. Various suppliers have developed high-CTE ceramic materials to be used as substrates for CBGA packaging. These high-CTE ceramic materials have a CTE that is more closely matched to that of FR-4, and hence, improves the solder joint reliability of the package when subject to thermal loading conditions encountered during field life. This study assessed the solder joint reliability of a CTE CBGA for use in a high availability network backbone router. A numerical technique based on fracture mechanics and energy methods was used to predict reliability under accelerated temperature cycling (ATC) conditions.

Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications

In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the top side and bottom side of the interposer, respectively. The interposer with chips is bonded on a BT substrate; the BT substrate is bonded on a PCB; and a metallic heat spreader is placed on and glued to the CPU chips back-side. Because a 3D IC SiP with TSVs is so complicate for modeling and very difficult for meshing, this study attempted to use the equivalent models of embedded TSV, bump/solder bond and metallic trace to simplify a detail 3D IC model. We introduced a slice model, that four stacked chips on an interposer and each chip has two heaters and TSVs, to verify the accuracy and feasibility of the equivalent model by comparing to the detail model, the results of both models show that they are in a good agreement. By using the equivalent model to simulate the studied 3D IC integrated SiP; we found the CPU temperature would be dominated by the cooling capability of a thermal module that attached on the heat spreader. As for the DRAM chips that underneath the interposer, it is inevitable to have a quite high temperature due to the temperature superposition effect and an obstructed heat flow path. In fact, the severely high temperature of the chips under an interposer should be the main thermal issue for such a 3D IC SiP because there is no easy thermal solution for these chips.

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

Materials effects on reliability of FC-PBGA packages for Cu/low-k chips

Reliability of the flip-chip plastic ball grid array (FC-PBGA) packages is highly dependent on the properties of the constituent components and the interface formed between them. The relative mechanical compliances and thermal mismatch between the silicon chip, the underfill material and the organic laminate substrate are particularly important to the design and performance the package. Strong coupling between the chip and the substrate can cause chip cracking, delamination of interlayer dielectrics (ILD), delamination of underfill and problems associated with BGA interconnection when the package is assembled to a printed circuit board (PCB). The problem became more severe as we migrate to the 90nm and 65nm silicon technology nodes where low-k ILD is widely used. Combined experimental and modeling methods were used to investigate the thermo-mechanical behavior and failure mechanisms controlling FC-PBGA package reliability. Materials effect of new generation of underfill materials was first studied for minimizing the chip-substrate thermo-mechanical coupling. Fully assembled FC-PBGA packages with various underfill materials were evaluated following a carefully designed analysis and screening flow. Thermo-mechanical response of the package was measured and analyzed using high resolution moire interferometry and numerical modeling techniques. Four-point bending test was also used to characterize interfacial fracture energy for the critical interface between die passivation and underfill material. The experiments and modeling were correlated with the JEDEC standard component-level reliability testing results. The combined experimental and numerical analysis confirmed our selection of the substrate, underfill and other package materials and demonstrated that significantly improved reliability of the flip-chip PBGA packages can be achieved by controlling thermo-mechanical coupling of the silicon die and the package, and by controlling various important interfaces within the package

Design optimization of a high performance FCAMP package for manufacturability and reliability

There are distinct advantages of using multi-chip modules for leveraging performance. There are also handicapping issues with respect to known good die, test access, and repairability/rework. An FCAMP, or flip chip and memory package, is a way of resolving some of these problems and mitigating yield and reliability risk. The FCAMP allows for a flip chip ASIC die, and packaged, tested at-speed, and burned-in memory components to be assembled onto a substrate. Using direct chip attach for the ASIC reduces the body size of the FCAMP substrate. CSP type of packaged memory allows for full testing prior to assembly. The FCAMP device used in this investigation contains a flip chip die and four custom packaged SRAM. The system is architected so that the bulk of the interconnect resides on the substrate. The challenges of this package are routability with acceptable signal integrity and power integrity, packaging thermal mechanical integrity, package co-planarity, and long term reliability. This paper presents an overall design methodology along with evaluation of materials and substrate selection. The impact of the underfill material selection, SRAM packaging technology, lid material, and lid design on package warpage and manufacturability will be discussed. Preliminary reliability results are presented.

Shear microprobing of chip-package interaction in advanced interconnect structures

Chip-package interaction has become an increasingly important concern due to higher reflow temperatures of Pb-free solders and the heterogeneous integration of materials with vastly different properties. In particular, shear stresses are common during the packaging process. In this study, a microprobe metrology system is used to assess the mechanics of advanced interconnect structures under shear loading. This allows for a better understanding of the robustness of interconnect structures and the stresses they can tolerate.

The implementation of ASIC packaging design and manufacturing technologies on high performance networking products

This paper briefly presents how silicon integration and advances in packaging technology have enabled higher performance networking products, and is followed by discussions of how a system-level integrated approach is needed to address the challenges of the next generation products. Different methodologies of integrating memory and ASIC using advanced packaging technologies at both package level and board-/system-level are presented. Both connector-based and SMT based system in package (SiP) solutions with either flip-chip bare-die or BGA technologies are evaluated. Impact of each technology on product designs at silicon, substrate, and board level, as well as the effects on product manufacturability and reliability are discussed.

Feasibility Study of a SiP for High Performance and Reliability Product Application

For specific applications, there can be significant performance advantages when using a SiP (system in package). With the proper silicon functional partitioning, well controlled interconnect medium, and well tuned interface design; the data bandwidth can be increased by both speed and width. The disadvantages of SiPs are increased risks in reliability, manufacturability, and difficulty with test access, repair, and rework. The subsystem within the package is a flipchip ASIC die, and four packaged memory components. This allows the memory to be tested at-speed and burned in prior to assembly in the SiP. The feasibility study resulted in a combination of physical design tradeoffs, and reliability assessment of a test vehicle. The substrates were evaluated for routability, signal and power integrity. A custom electrical interface was specified for the chips to maximize bandwidth of the system. Package coplanarity, thermal mechanical integrity, and long term reliability were also examined. Preliminary results were presented

Environmental Effects on Dielectric Films in Plastic Encapsulated Silicon Devices

Mechanical integrity of interlayer and intralayer dielectric films and its impact on interconnect reliability has become more important as critical dimensions in ultralarge-scale integrated circuits are continuously reduced and Cu interconnect, low-k dielectrics (Cu/low-k) are widely adopted for the new technology nodes. Mechanical integrity of the dielectric films and reliability of interconnect can be affected by the film deposition process, stresses from chip-packaging interaction (CPI) and environmental factors such as moisture and temperature exposure. In this study attention has been focused on understanding the moisture and temperature effects on reliability of dielectric films in plastic encapsulated silicon devices. Sensitivities to moisture and temperature induced damage in the dielectric films of the silicon devices were first evaluated using accelerated temperature and humidity stress conditions. Multiple stress conditions were used so the testing results could be applied to validate a physical acceleration model for the combined temperature and humidity stresses. Moisture diffusion in the silicon devices and their packages was then modeled using commercial finite element analysis (FEA) software. Moisture sorption and diffusion properties of the packaging materials were also characterized to support the moisture diffusion modeling. Moisture distribution in the plastic package was analyzed for both the accelerated stress conditions and the product use or storage environmental conditions. The effectiveness of the peripheral seal ring on the silicon device as a moisture barrier was also investigated. Finally, reliability of the silicon devices under typical and extreme product use or storage environment conditions was assessed using the moisture distribution results and the validated acceleration model.

Micromechanics and damage processes in interconnect structures

Packaging advanced silicon devices has become increasingly challenging because the effects of stresses exerted on interconnect structures during package assembly and operation are not well understood. In this study, a microprobe metrology system is used to assess the mechanics of these interconnect structures. This allows for a better understanding of the robustness of an interconnect design and the stresses that can be tolerated before damage initiation.