Peng Su

Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications

In this study, we used simulation technique to analyze the thermal behaviors and investigate the thermal issues of a designed system in package (SiP) for network system application that based on a three dimensional integrated circuit (3D IC) structure. The 3D IC SiP has an interposer which with regularly embedded through-silicon vias (TSVs); there are one CPU chip and two DRAM chips planted on the top side and bottom side of the interposer, respectively. The interposer with chips is bonded on a BT substrate; the BT substrate is bonded on a PCB; and a metallic heat spreader is placed on and glued to the CPU chips back-side. Because a 3D IC SiP with TSVs is so complicate for modeling and very difficult for meshing, this study attempted to use the equivalent models of embedded TSV, bump/solder bond and metallic trace to simplify a detail 3D IC model. We introduced a slice model, that four stacked chips on an interposer and each chip has two heaters and TSVs, to verify the accuracy and feasibility of the equivalent model by comparing to the detail model, the results of both models show that they are in a good agreement. By using the equivalent model to simulate the studied 3D IC integrated SiP; we found the CPU temperature would be dominated by the cooling capability of a thermal module that attached on the heat spreader. As for the DRAM chips that underneath the interposer, it is inevitable to have a quite high temperature due to the temperature superposition effect and an obstructed heat flow path. In fact, the severely high temperature of the chips under an interposer should be the main thermal issue for such a 3D IC SiP because there is no easy thermal solution for these chips.

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

A comparison study of electromigration performance of Pb-free flip chip solder bumps

The electromigration of flip chip solder joints is an ongoing reliability concern for manufacturers of integrated circuit (IC) components and electronic systems. As power levels of ICs continue to increase, current densities within individual solder bumps often increase, along with the operation temperatures of the die surface. Both of these factors have detrimental impact on the electromigration (EM) performance of the solder bumps, as they provide increased driving forces for the diffusion and dissolution of the under bump metallization (UBM) into the solder bumps. Additionally, these changes are occurring concurrently with the transition to Pb-free solder bumps for the next technology node. Compared to commonly used high-Pb bumps, Pb-free bumps typically have reduced lifetime with similar under bump metallization. In this study, a specially designed test vehicle was used to assess the EM performance of Pb-free solder bumps. Electroplated Sn2.6Ag solder bumps were tested with a variety of current density and temperature combinations. Lifetime data were collected for each of the conditions and a prediction model is established using Blacks equation. The results were also compared with previous work done on high-Pb and eutectic SnPb bumps using the same test vehicle. From this work, Pb-free solder bumps are shown to have slightly decreased lifetime compared to high-Pb bumps, but still significantly higher than eutectic SnPb solder bumps. With the correct design strategies, including optimized via opening sizes and under bump metallization materials, SnAg Pb-free bumps can provide sufficient reliability for a majority of application conditions.

Characterization of plasticity and stresses in TSV structures in stacked dies using synchrotron x-ray microdiffraction

The characteristics of thermal stresses in a five-stacked memory dies containing through-silicon vias (TSVs) were measured with synchrotron x-ray microdiffraction. The measurements were performed in and around the Cu vias for both the top and bottom dies. With scanning white beam x-ray microdiffraction, high resolution mappings of stress distribution were obtained. The results provided a direct observation of the local plasticity in Cu TSV and the stress and deformation in the surrounding Si. Thermo-mechanical modeling using finite element analysis (FEA) was carried out for the stacked structure. Results from the modeling analysis were correlated to the synchrotron observation to examine the effect of the die stacking on the stress behavior of the TSV at different die levels. Overall, the stress distribution obtained by FEA showed good agreement with the synchrotron measurement. The presence of plasticity was predicted by FEA and confirmed by the synchrotron observation. The implication of the residual stress on reliability of the memory structure was discussed. The results from this work demonstrate the capability of synchrotron based x-ray technique in studying the stress characteristics of multi-stack TSV structures.

Effects of reliability testing methods on microstructure and strength at the Cu wire-Al pad interface

As the adoption of Cu bond wires continues, increasing quantity of component families are being qualified by component suppliers using standard acceleration test methods and durations. While these tests provide a benchmark comparison with conventional technologies such as Au wire bonding, for users of these components for high-reliability applications, a frequent discussion on reliability assessment is which particular test would be the most practical or effective in detecting material and process issues. In this work, we evaluate the effects of bond wire material and process variations using three acceleration tests including autoclave, unbiased HAST, and biased-HAST. Both bare Cu and Pd-coated Cu wires are included and process variations are also introduced. The results from the acceleration tests and microstructure analysis of the failed components will offer insight into the effectiveness of these acceleration tests and responses of the various bond wire materials and bond processes.

A synchrotron micro-diffraction investigation of crystallographic texture of high-Sn alloy films and its effects on whisker growth

For electroplated Sn and Sn alloy finishes, one of the reliability concerns remains the risk of whisker growth. Results from recent work have suggested that whiskers are most likely to form in regions of the films where high stress or a stress gradient exists. If strain/stress distribution information can be collected at a grain-by-grain level, correlations between such information and the propensity of whisker growth can be further understood. In this work, we utilized a highly focused X-ray beam from a synchrotron source to perform micro-diffraction on a series of Sn and Sn-containing finishes. The high brightness and small beam size of the X-ray enabled the generation of grain-by-grain orientation map as well as the strain/stress levels in individual grains. The electroplated finishes analyzed included pure Sn, Sn-Cu, and Sn-Cu-Pb finishes with various concentrations of Cu and Pb. Plating current density was also varied for each finish composition and the textures of these finishes were compared. After plating, these finishes were stored at ambient condition and examined regularly for surface defect formation. Once hillock or whisker growth was observed, the areas surrounding the growth were scanned with the X-ray. Additionally, these samples were also analyzed with standard X-ray diffraction and inverse pole figures were generated to compare the texture of the samples. A finite element model was also generated to simulate the texture of the finishes. By implementing the stiffness matrix of the finishes, we were able to explicitly implement the variation of finish texture on a grain-by-grain basis, and thus assess the strain/stress distribution in the finish. The analytical and simulation results from this study suggest that plating process parameters such as current density have a significant impact on the crystallographic texture of the plated finishes. Under similar strain conditions, certain textures would generate higher stresses in the finishes and result in higher levels of whisker growth.

Effect of high temperature storage on the stress and reliability of 3D stacked chip

In this work, the effect of high temperature storage (HTS) on the stress in and around Cu TSVs in 3D stacked chips is studied by scanning white beam x-ray microdiffraction. The x-ray microdiffraction measurements were conducted on different die levels in the stacked chips before and after HTS test. High resolution mappings of stress distribution were obtained and compared between pre-HTS and post-HTS for both the Cu via and the surrounding Si. The x-ray microdiffraction technique provides a means for nondestructive, direct stress measurement in a 3D die stack structure. Finite element analysis (FEA) was carried out for the test structure to interpret the measurement results and to discuss the thermal aging effect on the 3D chip. Overall, the results show reduced stress in both Cu and Si after HTS, which can be explained by stress relaxation occurred during HTS. The implication of the HTS results on long term reliability of 3D die stacks is discussed.

An evaluation of effects of molding compound and substrate material properties on reliability of Cu wire BGA components

The transitions to copper (Cu) from gold (Au) bond wires is occurring for an increasingly broader range of semiconductor components. For ball grid array (BGA) packages, key packaging materials including molding compound and substrate all need to be re-evaluated as they may interact with Cu wire bond differently from Au wires and introduce new failure mechanisms. In this work, we investigate the impact of molding compound chemistry and halogen content of substrate on the reliability performance of an organic BGA package. For the molding compound, two material properties, pH level and C1-concentration are varied and a total of 9 formulations are generated. For substrates, a high-halogen substrate and a Halogen Free substrate are evaluated. Two types of acceleration tests, HTS (High Temperature Storage) test and biased-HAST (Highly Accelerated Stress Testing) are performed on the components. The effects of molding compound pH/C1-levels and substrate halogen content on the failure rates will be discussed. Additionally, analytical results on the failed components using FIB (Focus Ion Beam), SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy), and EDX (Energy Dispersive X-ray) will be reported. The reliability testing and analytical results will demonstrate the importance of controlling packaging material properties and provide guidelines for the selection of these materials. For high-reliability and mission-critical electronic systems, improved and better-controlled packaging material formulations will be needed to ensure the long-term reliability of components using Cu bond wires.

Investigation of thermo-mechanical stresses and reliability of 3D die-stack structures by synchrotron x-ray micro-diffraction

In this work, thermo-mechanical stresses and reliability of 3D die-stack structures developed for the Hybrid Memory Cube (HMC) technology are investigated using experiments and modeling analysis. Synchrotron x-ray micro-diffraction measurements are used to directly measure the stress distribution around Cu vias in different die levels. High resolution stress mappings are obtained and verified by finite element analysis (FEA). The FEA is applied to estimate the stress effect on device mobility changes and the warpage of the integrated structure.

An Evaluation of Effects of Molding Compound Properties on the Reliability of Ag Wire Bonded Components

Silver (Ag) bond wires are increasingly used in semiconductor components to replace gold (Au) bond wires, and applications for these components are expanding from consumer to high-reliability electronic systems. To assess the impact of this technology transition on the overall component reliability, extended reliability testing beyond the typical JEDEC component qualification testing is needed. Additionally, key packaging materials, such as molding compounds, also need to be re-evaluated as they may interact with the Ag wire bond differently from Au wire bonds and introduce new failure mechanisms under different conditions. In this work, we investigate the impact of molding compound chemistry and testing condition on the reliability performance by testing a range of commercially available Ag-wire bonded components. The composition of the molding compound is analyzed and concentrations of key elements that contribute to bond wire / bonding pad interface corrosion are reported. These components are subjected to acceleration tests, including temperature-humidity-bias and high-temperature storage tests. As a control, Au wire-bonded components are also subjected to the same acceleration tests. Failure rates and mechanisms for the experimental conditions are determined based on resistance measurements and cross-section analyses of microstructures and discussed in terms of interactions between the test conditions, the chemistry of the molding compounds, and wire bond composition. Reliability testing and analytical results demonstrate the importance of controlling molding compounds composition and properties and provide guidelines for the selection of these materials for different applications. In particular, improved and better-controlled packaging material formulations will be needed for high-reliability and mission-critical electronic systems to ensure the long-term reliability of components using Ag bond wires.