Mark Cravatts

A testbed for mobile networked computing

The rapid deployment of wireless access technology, along with the emergence of high speed integrated service networks, promises to provide users with ubiquitous access to multimedia information in the near future. We are building an experimental testbed system, SWAN (Seamless Wireless ATM Network), to mimic this emerging networking environment. Our wireless access network is organized according to a nanocellular design with base stations serving as a gateway for communication between the wired network and the mobile hosts in a cell. Normally, a mobile host sends and receives traffic through the base station in its current cell. But SWAN also supports direct ephemeral networking between a limited number of cooperating mobile hosts within a small domain. The heart of the testbed is a networking subsystem, FAWN (Flexible Adapter for Wireless Networking) that interfaces the standard PCMCIA bus to an RF modem. The FAWN interface is used with a PC or workstation connected to a wired backbone network or a portable device such as a laptop or palmtop computer. In addition, a user interface consisting of an LCD display, audio I/O, and a bar code reader has been built. When interfaced with FAWN this results in a portable wireless multimedia terminal.

Design of an active memory system for network applications

We describe an active memory named SWIM (Structured Wafer-based Intelligent Memory), designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to interact with a disk or a communication line through a backend port. A network or I/O subsystem is built using an interconnected ensemble of such memory logic pairs. A complex network processing task can now be distributed between a large number of small memory processors each doing a sub-task, while still retaining a transparent memory interface. We argue that active memory based processing enables more powerful, scalable and robust designs for storage and communications subsystems, that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year.<<ETX>>

An experimental active-memory-based network element

We describe a network element based on an active memory named SWIM (Structured Wafer-based Intelligent Memory), designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to interact with a disk or a communication line through a backend port. The processing logic is specially designed to perform operations such as pointer dereferencing, memory indirection, searching and bounds checking efficiently. The network element is built using an interconnected ensemble of such memory logic pairs. A complex processing task can now be distributed between a large number of small memory processors each doing a sub-task, while still retaining a common locus of control in the host CPU for higher level administrative and provisioning functions. We argue that active memory based processing enables more powerful, scalable and robust designs for storage and communications subsystems, that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year.<<ETX>>

An experimental active memory based I/O subsystem

We describe an I/O subsystem based on an active memory called SWIM, designed for efficient storage and manipulation of data structures. The key architectural idea in SWIM is to put some processing logic inside each memory chip that allows it to perform data manipulation operations locally and to communicate with a disk or a communication line through a backend port. The processing logic is specially designed to perform operations such as pointer dereferencing, memory indirection, searching and bounds checking efficiently. The I/O subsystem is built using an interconnected ensemble of such memory logic pairs. This allows a complex I/O task to be distributed between a large number of small memory processors each doing a sub-task, while still retaining a common locus of control for higher level functions. This enables more powerful, scalable and robust designs for storage and communications subsystems that can support emerging network services, multimedia workstations and wireless PCS systems. A complete parallel hardware and software system constructed using an array of SWIM elements has been operational for over a year. We present the application of SWIM to three network functions that we have currently implemented: a national phone database server, a high performance IP router, and a call screening agent.