Mark D. Kellam

A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications

A power-efficient 6.25Gb/s transceiver in 90nm CMOS for chip-to-chip communication is presented, it dissipates 2.2mW/Gb/s operating at a BER of <10-15 over a channel with -15dB attenuation at 3.125GHz. A shared LC-PLL, resonant clock distribution, a low-swing voltage-mode transmitter, a low-power phase rotator, and a software-based CDR and an adaptive equalizer are used to reduce power

Relaxation Effect in RRAM Arrays: Demonstration and Characteristics

In this letter, two distinct retention degradation regions, a rapid resistance relaxation effect followed by a slow resistance loss process, were observed from high-resistance state (HRS) of HfOx-based resistive random access memory (RRAM) array retention tests. The influence of resistance, thickness of HfOx, baking temperature, and RESET pulsewidth on the relaxation effect for HRS were studied in detail. Random telegraph noise (RTN) characterization suggests that this early loss of data for HRS is due to new oxygen vacancies generation which could shorten the gap between the filament and the TaOx layer. Possible causes were provided to describe the relaxation effect and to understand the RTN characteristics correlated with relaxation effect in RRAM array.

HfO2/Al2O3 multilayer for RRAM arrays: a technique to improve tail-bit retention

In this work, the HfO2/Al2O3 multilayer structure is applied for RRAM arrays. Compared to HfO2 RRAM, the data retention failure of tail bits is suppressed significantly, especially for the high resistance state (HRS). The retention of tail bits is studied in detail by temperature simulation and crystallization analysis. We attribute the improvement of tail-bit retention to the decreased oxygen ion diffusivity caused by the Al2O3 layer. Furthermore, the HfO2/Al2O3 multilayer structure exhibits higher crystallization temperature, thus leading to fewer grain boundaries around the filament during the operations. With fewer grain boundaries, oxygen ion diffusion is suppressed, leading to fewer tail bits and better retention.

Computational diffractive imager with low-power image change detection

We describe a hardware implementation of an ultra-miniature lensless diffraction-based CMOS computational sensor/imager that supports robust low-power on-sensor image change detection and data streaming modes. Such sensors have numerous applications in surveillance, machine inspection and human interface.

Reducing electrical power dissipation in computational imaging systems through special-purpose optics

In computational sensing and imaging, optics can perform some of the processing tasks traditionally performed by digital signal processing and, conversely, digital signal processing can perform some of the processing tasks traditionally performed by optics. This approach thus provides a new framework for reducing electrical power dissipated by sensors: for a criterion end-to-end functional performance, design the optics such that the digital computation cost is as low as possible. There are two such strategies to designing optics to reduce electrical power dissipation: creating optics that produce an optical signal that either 1) requires less digital processing for the criterion functional performance or 2) requires fewer pixels and hence less read, A/D conversion, and signal transfer power. A special-purpose diffractive optical element integrated with a CMOS image sensor photodetector array with simple on-chip processing reveal power reduction in one operational mode roughly two orders of magnitude compared to that in a functionally equivalent traditional lens-based sensors.

Suppression of relaxation effect in HfO2 resistive random access memory array by improved program operations

As a postprograming resistance shift, the relaxation effect could be a major issue for resistive random access memory (RRAM) applications. To understand the physical mechanisms of the relaxation effect, temperature-related ion and charge movements are analyzed using the incremental-step-pulse program (ISPP) and repeat-cycle program (RCP). Pre-electron detrapping (PED) operation is found to minimize the amount of interfacial trapped charges and thus to greatly reduce the resistance relaxation effect. Our experimental results demonstrate the improved data retention and tight distribution of RRAM arrays as a result of the above optimized program operations.