Gary B. Bronner

Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications. >

Array pass transistor design in trench cell for Gbit DRAM and beyond

Aggressive scaling of the DRAM cell size requires minimum dimensions in both the channel length and the channel width of the array pass transistor. As a result of the stringent leakage current requirement, the design for the array MOSFET becomes increasingly challenging as cell size is reduced. In this paper, we present data that illustrate the importance of the channel and the source/drain engineering, along with considerations of minimizing the junction leakage. By utilizing a 512 k array diagnostic monitor, a methodology is presented for optimum array cell design in a statistically reliable manner. Design issues unique to the trench capacitor cell are covered. Alternative biasing schemes that boost the process window are also discussed.

A 4 Mb Low-temperature DRAM

The authors present the characterization of the first dynamic RAM (DRAM) fabricated in a technology specifically optimized for cryogenic operation. With the power supply adjusted to assure hot-electron reliability, the 25-ns 4-Mb low-temperature (LT) chips operated 3 times faster than conventional chips. The LT-optimized chips functioned properly with cycle times as fast as 45 ns, and with a toggle-mode data rate of 667 Mb/s. Wide operating margins and a very large process window for data retention were demonstrated. At a temperature of 85 K the storage retention time of the trench-capacitor memory cells exceeded 8 h. This study shows that the performance leverage offered by low temperature applies equally well to DRAM and to logic. There is no limitation inherent to memory. >

On the retention time distribution of dual-channel vertical DRAM technologies

In this paper, we discuss unique opportunities in vertical transistor DRAM technology for retention time optimization. By fully utilizing the asymmetric vertical device design, we demonstrate that shallow Arsenic bitline junction, reduced buried strap outdiffusion, and locally lowered p-well concentration can be incorporated in vertical DRAM transistors to pave the scaling path without degrading retention time. A methodology to probe storage node side leakage current by the use of gated-diode measurements is established. Various mechanisms that impact retention time distribution are discussed. Furthermore, we demonstrate that the degradation of tail retention time due to high junction electric field can be minimized by aggressively lowering the junction depletion volume and defect levels.

Gate prespacers for high density DRAMs

The channel length of the DRAM transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device. There is thus a need for novel integration schemes that allow the continued cell shrinkage with only limited shrinking of the channel length. In this paper, we present an integration scheme which allows for a larger gate polysilicon length for a given pitch thus improving array device leakage (by about one generation) for a given technology.

Technologies for scaling vertical transistor DRAM cells to 70 nm

Vertical transistor DRAM cells have been demonstrated as viable in the 110 nm generation. This paper describes the issues associated with scaling these cells to the 70 nm node and demonstrates fixes to all known issues. Scaling to 70 nm is possible through the development of two key enabling technologies, high aspect ratio STI fill and low resistance metal deep trench fill, and through minor cell modification. Each of these items are addressed and shown to be viable using a functional 512 Mb prototype DRAM chip at 110 nm half-pitch groundrule. Based on these results, we believe the vertical transistor DRAM cell is one of the most promising for continued scaling of conventional DRAM and embedded DRAM cells.

Threshold voltage roll-up/roll-off characteristic control in sub-0.2-/spl mu/m single workfunction gate CMOS for high-performance DRAM applications

Threshold voltage (V/sub t/) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-/spl mu/m single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N/sub 2/ implant prior to gate oxidation is important to reduce V/sub t/ roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V/sub t/ roll-off characteristics. Finally, the impact of halo implant on V/sub t/ variation in sub-0.2-/spl mu/m buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V/sub t/ variation in sub-0.2-/spl mu/m single workfunction gate pFET.

Optimization of silicon technology for the IBM system z9

IBM 90-nm silicon-on-insulator (SOI) technology was used for the key chips in the System z9TM processor chipset. Along with system design, optimization of some critical features of this technology enabled the z9TM to achieve double the system performance of the previous generation. These technology improvements included logic and SRAM FET optimization, mask fabrication, lithography and wafer processing, and interconnect technology. Reliability improvements such as SRAM optimization and burn-in reliability screen are also described.

Vertical pass transistor design for sub-100 nm DRAM technologies

The 8F/sup 2/ vertical transistor DRAM cell is a cost-efficient, litho-friendly structure suitable for scaling to sub-100 nm ground rules. In this paper, we report on device design considerations for vertical pass transistors used in ultra-dense DRAM technologies. A double-gate, vertical DRAM pass transistor that meets 1fA off-current requirement and offers twice the current drive of comparable 175 nm planar devices will be presented. Additionally, structural features unique to vertical devices are highlighted.