Mark Edward Dean

Self-timed logic using current-sensing completion detection (CSCD)

This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: (1) reduced parasitic capacitance, (2) removal of spacer tokens in the data stream, and (3) computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison.

The design of a high-performance cache controller: a case study in asynchronous synthesis

The authors integrated two distinct approaches in asynchronous system design: the design of controllers and the design of processor architectures. In earlier work, S.M. Nowick and D.L. Dill (1991) presented a new method for the synthesis of locally clocked asynchronous controllers, and the STRiP architecture was shown by M.E. Dean (1992) to provide an attractive alternative to comparable synchronous and asynchronous implementations. However, to support this asynchronous paradigm, an efficient asynchronous memory subsystem is critical. Here, the locally clocked synthesis method is applied to the design of an asynchronous second-level cache controller. The authors demonstrate the feasibility of the proposed locally clocked method for the design of a substantial real-world controller, show how such a controller can support the asynchronous external interface of an asynchronous RISC architecture, and present a cache controller which is significantly faster than a comparable synchronous design. Cache-access latency in the design is 50% less than for an equivalent synchronous implementation. >

Self-timed logic using Current-Sensing Completion Detection (CSCD)

This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allows self-timed circuits to be designed using single-rail variable encoding (one signal wire per logic variable) and implemented in about the same silicon area as an equivalent synchronous implementation. Compared to dual-rail encoding methods, CSCD can reduce the number of signal wires and transistors used by approximately 50%. CSCD implementations improved performance over equivalent dual-rail designs because of: (1) reduced parasitic capacitance, (2) removal of spacer tokens in the data stream, and (3) computation state similarity of consecutive data variables. Several CSCD configurations are described and evaluated and transistor-level implementations are provided for comparison.

Experience with building a commodity intel-based ccNUMA system

Commercial cache-coherent nonuniform memory access (ccNUMA) systems often require extensive investments in hardware design and operating system support. A different approach to building these systems is to use Standard High Volume (SHV) hardware and stock software components as building blocks and assemble them with minimal investments in hardware and software. This design approach trades the performance advantages of specialized hardware design for simplicity and implementation speed, and relies on application-level tuning for scalability and performance. We present our experience with this approach in this paper. We built a 16-way ccNUMA Intel system consisting of four commodity four-processor Fujitsu® Teamserver™ SMPs connected by a Synfinity™ cache-coherent switch. The system features a total of sixteen 350-MHz Intel® Xeon™ processors and 4 GB of physical memory, and runs the standard commercial Microsoft Windows NT® operating system. The system can be partitioned statically or dynamically, and uses an innovative, combined hardware/software approach to support application-level performance tuning. On the hardware side, a programmable performance-monitor card measures the frequency of remote-memory accesses, which constitute the predominant source of performance overhead. The monitor does not cause any performance overhead and can be deployed in production mode, providing the possibility for dynamic performance tuning if the application workload changes over time. On the software side, the Resource Set abstraction allows application-level threads to improve performance and scalability by specifying their execution and memory affinity across the ccNUMA system. Results from a performance-evaluation study confirm the success of the combined hardware/software approach for performance tuning in computation-intensive workloads. The results also show that the poor local-memory bandwidth in commodity Intel-based systems, rather than the latency of remote-memory access, is often the main contributor to poor scalability and performance. The contributions of this work can be summarized as follows: • The Resource Set abstraction allows control over resource allocation in a portable manner across ccNUMA architectures; we describe how it was implemented without modifying the operating system. • An innovative hardware design for a programmable performance-monitor card is designed specifically for a ccNUMA environment and allows dynamic, adaptive performance optimizations. • A performance study shows that performance and scalability are often limited by the local-memory bandwidth rather than by the effects of remote-memory access in an Intel-based architecture.

Spatiotemporal Classification Using Neuroscience-Inspired Dynamic Architectures

Abstract We discuss a neuroscience-inspired dynamic architecture (NIDA) and associated design method based on evolutionary optimization. NIDA networks designed to perform anomaly detection tasks and control tasks have been shown to be successful in previous work. In particular, NIDA networks perform well on tasks that have a temporal component. We present methods for using NIDA networks on classification tasks in which there is no temporal component, in particular, the handwritten digit classification task. The approach we use for both methods produces useful subnetworks that can be combined to produce a final network or combined to produce results using an ensemble method. We discuss how a similar approach can be applied to other problem types.

Neuroscience-inspired inspired dynamic architectures

Neuroscience-inspired computational elements and architectures are one of the most popular ideas for replacing the von Neumann architecture. In this work, we propose a neuroscience-inspired dynamic architecture (NIDA) and discuss a method for automatically designing NIDA networks to accomplish tasks. We discuss the reasons we chose evolutionary optimization as the main design method and propose future directions for the work.

An Application Development Platform for Neuromorphic Computing

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic computing systems developed as a hardware based approach to the implementation of neural networks. They feature highly adaptive and programmable structural elements, which model artificial neural networks with spiking behavior. We design them to solve problems using evolutionary optimization. In this paper, we highlight the current hardware and software implementations of DANNA, including their features, functionalities and performance. We then describe the development of an Application Development Platform (ADP) to support efficient application implementation and testing of DANNA based solutions. We conclude with future directions.

A VLSI Design for Neuromorphic Computing

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that exhibit spiking behaviors and can be designed using evolutionary optimization. Array elements are rapidly reconfigurable and can function as either neurons, synapses or fan-out elements with programmable interconnections and parameters. Currently, DANNAs are implemented using Field Programmable Gate Arrays (FPGAs) and are constrained in capacity and performance by this technology. To alleviate these constraints and introduce new and improved features, a semi-custom Very Large Scale Integration (VLSI) design has been created. This VLSI design improves upon the FPGA implementations in three key areas: 50x improvement in element capacity, 10x improvement in clock speed, and a significant reduction in power consumption. Finally, the VLSI design allows for near real time monitoring of the individual elements in the array.

Visual analytics for neuroscience-inspired dynamic architectures

We introduce a visual analytics tool for neuroscience-inspired dynamic architectures (NIDA), a network type that has been previously shown to perform well on control, anomaly detection, and classification tasks. NIDA networks are a type of spiking neural network, a non-traditional network type that captures dynamics throughout the network. We demonstrate the utility of our visualization tool in exploring and understanding the structure and activity of NIDA networks. Finally, we describe several extensions to the visual analytics tool that will further aid in the development and improvement of NIDA networks and their associated design method.

Extensions and enhancements for the DANNA neuromorphic architecture

Dynamic Adaptive Neural Network Arrays (DANNAs) are neuromorphic systems that have been developed for hardware implementation. They feature highly adaptive and programmable structural elements, which model artificial neural networks with spiking behavior. In this paper, we highlight the current hardware implementations of DANNA, including their features and functionalities. We conclude with future directions.