Mark F. Bocko

On the security and robustness of encryption via compressed sensing

The compressed sensing (CS) paradigm unifies sensing and compression of sparse signals in a simple linear measurement step. Reconstruction of the signal from the CS measurements relies on the knowledge of the measurement matrix used for sensing. Generation of the pseudo-random sensing matrix utilizing a cryptographic key, offers a natural method for encrypting the signal during CS. This CS based encryption has the inherent advantage that encryption occurs implicitly in the sensing process - without requiring additional computation. Additionally, the robustness of recovery from compressed sensing, allows a new form of ldquorobust encryptionrdquo for multimedia data, wherein the signal is recoverable with high fidelity despite the introduction of additive noise in the encrypted data. In this paper, we examine the security and robustness of this CS based encryption method. The security implications are investigated by considering brute force and structured attacks. Robustness is characterized empirically. Our analysis and results indicate that the computational complexity of these attacks renders them infeasible in practice. In addition, the CS based encryption is found to have fair robustness against additive noise, making it a promising ldquorobust encryptionrdquo technique for multimedia.

Prospects for quantum coherent computation using superconducting electronics

We discuss the prospects and challenges for implementing a quantum computer using superconducting electronics. It appears that Josephson junction devices operating at milli-Kelvin temperatures can achieve a quantum dephasing time of milliseconds, allowing quantum coherent computations of 10/sup 10/ or more steps. This figure of merit is comparable to that of atomic systems currently being studied for quantum computation.

An interface circuit for measuring capacitance changes based upon capacitance-to-duty cycle (CDC) converter

We present a direct-to-digital capacitive sensor readout circuit that converts capacitance changes of a sensor element to changes of the duty cycle of a square-wave oscillator, which, in turn, is converted to a digital output by a counter. The readout circuit resembles a single-slope analog-to-digital converter structure. There are several advantages of this readout scheme. First, due to its simplicity and low number of components, the power consumption of the circuit is expected to be significantly smaller than in similar digital readout designs. Furthermore, linearization of the output may be achieved using an EEPROM lookup table. Another advantage is the possibility of performing adaptive measurements where the sensor resolution and bandwidth may be changed via the readout circuit software. Finally, we present a theory of the adaptive measurement and an analysis of the design tradeoffs. The capacitance-to-duty cycle readout circuit may achieve large bandwidth and high resolution in a modern low-voltage, low-power CMOS implementation. The performance of a prototype readout circuit built from discrete components is 13-bit effective resolution with a 1-kHz bandwidth.

Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling

We present a theoretical analysis, design, and experimental characterization of a CMOS image sensor with pixel-level ΣΔ oversampling analog-to-digital conversion (ADC). The design employs five transistors per-pixel to implement a charge-based ΣΔ ADC at each pixel. In the current design a dynamic regenerative latch comparator is divided into an input transistor, which is contained within each pixel, and the remaining comparator structure shared among the pixels of each column. A charge feedback digital-to-analog converter (DAC) is implemented at each pixel with a three-transistor structure. As opposed to more traditional CMOS image sensors, this image sensor architecture is suitable for implementations in advanced low supply voltage CMOS technologies since its dynamic range is not affected by the reduction of the pixel reset voltage. In addition, similar to the readout methods in low power random access memory designs, this pixel readout architecture does not employ any active amplifiers which allows for low static power operation. Experimental characterization of a prototype fabricated in a 0.35 μm silicided CMOS technology is presented. The estimated power consumption of the fully integrated 128 × 128 imager including decimation filters and I/O interface is 60 nW/pixel at 30 frames per second for 8-bits per-pixel. A peak signal-to-noise ratio of 52 dB and intra-scene dynamic range of 74 dB were measured. The dynamic range was extended to 91 dB through control of the in-pixel DAC supply voltage over the range of 0.8 V-3.3 V.

\Sigma\Delta

We introduce a set theoretic framework for watermarking. Multiple requirements, such as watermark embedding strength, imperceptibility, robustness to benign signal processing, and fragility under malicious attacks are described as constraint sets and a watermarked image is determined as a feasible solution satisfying these constraints. We illustrate that several constraints can be formulated as convex sets and develop a watermarking algorithm based on the method of projections onto convex sets. The framework allows flexible incorporation of different constraints, including embedding strength requirements for multiple watermarks that share the same spatial context and different imperceptibility requirements based on frequency-weighted error and local texture perceptual models. We illustrate the effectiveness of the framework by designing a hierarchical semifragile watermark that is tolerant to mild compression, allows tamper localization, and is fragile under aggressive compression. Using a quad-tree representation, a spatial resolution hierarchy is established on the image and a watermark is embedded corresponding to each node of the hierarchy. The spatial hierarchy of watermarks provides a graceful tradeoff between robustness and localization under mild JPEG compression, where watermarks at coarser levels demonstrate progressively higher immunity to JPEG compression. Under aggressive compression, watermarks at all hierarchy levels vanish, indicating a lack of trust in the image data. The constraints implicitly partition watermark power in the resolution hierarchy as well as among image regions based on robustness and invisibility requirements. Experimental results illustrate the flexibility and effectiveness of the method

Analog-to-Digital Conversion

We have developed a high speed test scheme for RSFQ circuits, in order to measure the maximum clock frequency of a four-bit RSFQ decimation digital filter (simulated to be 11 GHz). Our high speed test requires only a low speed interface and standard low-cost measurement equipment. Three auxiliary test units built of simple RSFQ circuits are used. A circular JTL structure generates an on-chip high speed clock with frequency adjustable from 4 to 16 GHz. A pseudo-random number generator with period 64 clock cycles provides parallel input to the filter. Finally, 12 four-bit acquisition shift registers collect output data. We have integrated all the above units on a single chip. The chip is initialized at low speed, run at high speed, and read out at low speed. Our testing scheme is superior to previously reported high-speed tests in the area of the added circuitry, in the requirements on high-speed input/output, in control, and in the parameters of the measurement equipment. The scheme can be easily adapted to test various RSFQ circuits.

A Set Theoretic Framework for Watermarking and Its Application to Semifragile Tamper Detection

We consider the capabilities of the tunneling probe of the scanning tunneling microscope as a displacement sensor as distinguished from its better established application to surface imaging. Electromechanical transducers that operate on this principle can achieve very large gain and a noise temperature equal to the minimum required by quantum mechanics for any linear amplifier. We present a two‐port network representation of the tunneling transducer, including noise, that allows us to discuss the differences between the tunneling transducer and more conventional electromechanical transducers and to draw analogies between a tunneling transducer and a transistor. We present a simple equivalent circuit for the tunneling transducer including two uncorrelated noise generators, the tunneling current shot noise and the fluctuating force that the tunneling probe exerts on a test mass. In practice the fluctuating ‘‘back action’’ force spectral density is exceedingly small. We give an example of a system in which a...

High speed testing of a four-bit RSFQ decimation digital filter

Abstract According to quantum theory, microscopic objects exist in a superposition of distinct states until they are “observed”. Nobody knows whether such quantum coherence can actually exist in a macroscopic system. In the experiment described here, a superconducting quantum interference device is extremely well isolated from any interaction with internal or external modes, and a superposition state can be demonstrated even if it lasts for less than 1 ns. This is accomplished by using superconducting digital electronic circuitry as the experimental apparatus. If successful, it is the first step toward a future full-scale quantum computer fabricated using integrated circuit manufacturing techniques.

The scanning tunneling microscope as a high‐gain, low‐noise displacement sensor

We have designed and RSFQ multiplier-accumulator, the central component of our decimation digital filter. The circuit consists of 38 synchronous RSFQ cells of six types arranged into a rectangular systolic array fed by one parallel input and one serial input. Timing is based on counter-flow clock distribution scheme with simulated maximum clock frequency of 11 GHz. The circuit, fabricated at Hypres, Inc., contains 1100 Josephson junctions, has power consumption less than 0.2 mW, and area less than 2.5 mm/sup 2/. The multiplier-accumulator has been tested at low frequency demonstrating full functionality and stable operation over a 24 hour testing period. This four-bit multiplier accumulator is one of the largest reported RSFQ circuits verified experimentally to date.

A realistic experiment to demonstrate macroscopic quantum coherence

We propose an analog CMOS image sensor with 10X faster readout settling time than standard active pixel sensor (APS) designs. The pixel in the proposed design is a standard APS source follower configuration thus retaining high fill factor. Negative feedback is applied to the readout of the pixel from a column shared circuit to increase its current driving capabilities and thereby reduce the settling time between correlated double sampling (CDS) samples, which significantly reduces the 1/f noise contributed by the in-pixel source follower transistor. In addition, we describe an improved active reset utilizing the current sensing method. We present analysis and simulations of the proposed current sensing active pixel (CSAP) sensor design in a standard 0.35 um CMOS process operating from a 3.3 V power supply.