Zeljko Ignjatovic

An interface circuit for measuring capacitance changes based upon capacitance-to-duty cycle (CDC) converter

We present a direct-to-digital capacitive sensor readout circuit that converts capacitance changes of a sensor element to changes of the duty cycle of a square-wave oscillator, which, in turn, is converted to a digital output by a counter. The readout circuit resembles a single-slope analog-to-digital converter structure. There are several advantages of this readout scheme. First, due to its simplicity and low number of components, the power consumption of the circuit is expected to be significantly smaller than in similar digital readout designs. Furthermore, linearization of the output may be achieved using an EEPROM lookup table. Another advantage is the possibility of performing adaptive measurements where the sensor resolution and bandwidth may be changed via the readout circuit software. Finally, we present a theory of the adaptive measurement and an analysis of the design tradeoffs. The capacitance-to-duty cycle readout circuit may achieve large bandwidth and high resolution in a modern low-voltage, low-power CMOS implementation. The performance of a prototype readout circuit built from discrete components is 13-bit effective resolution with a 1-kHz bandwidth.

An energy conservation method for wireless sensor networks employing a blue noise spatial sampling technique

In this work, we present a method for the selection of a subset of nodes in a wireless sensor network whose application is to reconstruct the image of a (spatially) bandlimited physical value (e.g., temperature). The selection method creates a sampling pattern based on blue noise masking and guarantees a near minimal number of activated sensors for a given signal-to-noise ratio. The selection method is further enhanced to guarantee that the sensor nodes with the least residual energy are the primary candidates for deselection, while enabling a tradeoff between sensor selection optimality and balanced load distribution. Simulation results show the effectiveness of these selection methods in improving signal-to-noise ratio and reducing the necessary number of active sensors compared with simpler selection approaches.

Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling

We present a theoretical analysis, design, and experimental characterization of a CMOS image sensor with pixel-level ΣΔ oversampling analog-to-digital conversion (ADC). The design employs five transistors per-pixel to implement a charge-based ΣΔ ADC at each pixel. In the current design a dynamic regenerative latch comparator is divided into an input transistor, which is contained within each pixel, and the remaining comparator structure shared among the pixels of each column. A charge feedback digital-to-analog converter (DAC) is implemented at each pixel with a three-transistor structure. As opposed to more traditional CMOS image sensors, this image sensor architecture is suitable for implementations in advanced low supply voltage CMOS technologies since its dynamic range is not affected by the reduction of the pixel reset voltage. In addition, similar to the readout methods in low power random access memory designs, this pixel readout architecture does not employ any active amplifiers which allows for low static power operation. Experimental characterization of a prototype fabricated in a 0.35 μm silicided CMOS technology is presented. The estimated power consumption of the fully integrated 128 × 128 imager including decimation filters and I/O interface is 60 nW/pixel at 30 frames per second for 8-bits per-pixel. A peak signal-to-noise ratio of 52 dB and intra-scene dynamic range of 74 dB were measured. The dynamic range was extended to 91 dB through control of the in-pixel DAC supply voltage over the range of 0.8 V-3.3 V.

\Sigma\Delta

We propose an analog CMOS image sensor with 10X faster readout settling time than standard active pixel sensor (APS) designs. The pixel in the proposed design is a standard APS source follower configuration thus retaining high fill factor. Negative feedback is applied to the readout of the pixel from a column shared circuit to increase its current driving capabilities and thereby reduce the settling time between correlated double sampling (CDS) samples, which significantly reduces the 1/f noise contributed by the in-pixel source follower transistor. In addition, we describe an improved active reset utilizing the current sensing method. We present analysis and simulations of the proposed current sensing active pixel (CSAP) sensor design in a standard 0.35 um CMOS process operating from a 3.3 V power supply.

Analog-to-Digital Conversion

We present a method to increase the resolution and stability of /spl Sigma//spl Delta/ analog to digital converters in which the entire /spl Sigma//spl Delta/ modulator is enclosed in a chopper-stabilization (CHS) structure. Simulations of the proposed architecture show that the effects of integrator opamp non-idealities (1/f noise, DC offset and drift) and digital-to-analog converter (DAC) DC offset and even-order distortion harmonics are eliminated and that the effect of integrator saturation distortion is reduced by up to 27dB in comparison to existing designs. Finally, the proposed architecture may be realized in a single-ended design enabling area-conservative circuit layouts.

CMOS image sensor readout employing in-pixel transistor current sensing

We describe a CMOS image sensor employing pixel-level SigmaDelta analog to digital conversion. The design has high fill factor (31%), zero DC offset fixed pattern noise and reduced reset and transistor readout noise in comparison to other analog and digital imager readout techniques. The SigmaDelta pixel design also has low power consumption: 0.88 nW/pixel at 30 fps, high dynamic range of 16 bits, intrinsic linearity, and relative insensitivity to process variations

Sigma-delta analog to digital converter architecture based upon a modulator design employing a mirrored integrator

A 2.5-GHz phase-locked loop (PLL) employing a low-power active switched-capacitor loop filter is presented. A subthreshold inverter-based active loop filter is presented and analyzed. Advantages such as type-II loop dynamics, low reference spurs, and small on-chip capacitors are achieved. In addition, 1/f noise of the inverter amplifier can be suppressed by the filters auto-zeroing operation. The prototype is designed and fabricated in a 0.18- μm CMOS technology. Measurement results show phase noise of -86 dBc/Hz at a 100-kHz offset, -124.0 dBc/Hz at a 3-MHz offset, and a reference spur level of -64 dBc. The PLL consumes about 16 mW with 0.46 mW dedicated to the loop filter active components.

A 0.88nW/pixel, 99.6 dB Linear-Dynamic-Range Fully-Digital Image Sensor Employing a Pixel-Level Sigma-Delta ADC

We present a complementary metal-oxide semiconductor (CMOS) image sensor with non-uniform pixel placement that enables a highly efficient calculation of the discrete cosine transform (DCT), which is the most mathematically intensive step of an image compression algorithm. This technique is based on the arithmetic Fourier transform (AFT), which has been shown to be five times more computationally efficient than DCT derivation methods commonly used. In this paper, the focus is on the basic theory and algorithm as well as the sensitivity of the method to image sensor fixed pattern noise (FPN). The architecture and circuits have been implemented in a conventional CMOS process. The method has been demonstrated in the current prototype and results that enable an assessment of the sensitivity to FPN have been obtained.

A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter

In this paper we describe an image sensor with nonuniform pixel placement that enables a highly efficient computation of the discrete cosine transform, which is the most computationally demanding step of the image compression algorithm. This technique is based on the arithmetic Fourier transform (AFT), which we show to be 5 times more computationally efficient than currently used DCT computation methods. The architecture and circuits described can be implemented in conventional CMOS processes.

Non-Uniformly Tiled CMOS Image Sensors for Efficient On-Chip Image Compression

An image sensor design with pixel-level sigma-delta (ΣΔ) conversion employing four transistors at each pixel where the feedback charge transfer is realized through the parasitic capacitances of an inactive transistor is presented. This architecture is a relatively simple and robust design where the only analog components required outside of the pixel array are shared row comparators and a voltage mode digital-to-analog converter (DAC) to supply the in-pixel charge feedback structures. The photodiode acts as the integrator of the ΣΔ modulator and an in-pixel charge feedback DAC is realized with two PMOS transistors. A third, minimum size PMOS transistor operating in the cut-off region provides capacitive coupling through which a controlled amount of charge is injected to the photodiode. The sensitivity of the image sensor is determined by the size of the feedback charge packets in the ΣΔ modulator. The remainder of the image sensor is all digital, including a decimation filter to convert each pixels single bit output stream into a multi-bit sample. We fabricated a test pixel structure in the TSMC-0.35µm CMOS technology with 10µm × 10µm pixels and a fill factor of 31%. Experimental results demonstrated a SNR of 60dB and a dynamic range of 83dB.