Mark F. Flanagan

Linear-Programming Decoding of Nonbinary Linear Codes

A framework for linear-programming (LP) decoding of nonbinary linear codes over rings is developed. This framework facilitates LP-based reception for coded modulation systems which use direct modulation mapping of coded symbols. It is proved that the resulting LP decoder has the ldquomaximum-likelihood (ML) certificaterdquo property. It is also shown that the decoder output is the lowest cost pseudocodeword. Equivalence between pseudocodewords of the linear program and pseudocodewords of graph covers is proved. It is also proved that if the modulator-channel combination satisfies a particular symmetry condition, the codeword error rate performance is independent of the transmitted codeword. Two alternative polytopes for use with LP decoding are studied, and it is shown that for many classes of codes these polytopes yield a complexity advantage for decoding. These polytope representations lead to polynomial-time decoders for a wide variety of classical nonbinary linear codes. LP decoding performance is illustrated for ternary Golay code with ternary phase-shift keying (PSK) modulation over additive white Gaussian noise (AWGN), and in this case it is shown that the performance of the LP decoder is comparable to codeword-error-rate-optimum hard-decision-based decoding. LP decoding is also simulated for medium-length ternary and quaternary low-density parity-check (LDPC) codes with corresponding PSK modulations over AWGN.

Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes

In a recent paper, a method was proposed to accelerate the majority logic decoding of difference set low density parity check codes. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be error-free, the average decoding time is greatly reduced. In this brief, we study the application of a similar technique to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one step majority logic decodable. The results obtained show that the method is also effective for EG-LDPC codes. Extensive simulation results are given to accurately estimate the probability of error detection for different code sizes and numbers of errors.

A Versatile Variable Rate LDPC Codec Architecture

This paper presents a system architecture for low-density parity-check (LDPC) codes that allows dynamic switching of LDPC codes within the encoder and decoder without hardware modification of these modules. Thus, rate compatibility is facilitated without the performance degradation inherent in a puncture-based system. This versatility also allows the LDPC system to be used in a variety of applications since the encoder and decoder can be used with codes that span a wide range of lengths and rates.

Iterative Channel Estimation, Equalization, and Decoding for Pilot-Symbol Assisted Modulation Over Frequency Selective Fast Fading Channels

A pilot-based channel estimation scheme is proposed for frequency selective Rayleigh fading channels which work in conjunction with the existing paradigm of turbo equalization. The iterative nature of the channel estimation technique provides substantial gain over noniterative methods and makes it a suitable choice for iterative equalization and decoding. The channel estimator has low complexity, is decoupled from the equalizer soft-input soft-output module, and is capable of tracking significant channel variations within a codeword. The scheme is compatible with quadratic-amplitude modulation and with both parallel concatenated convolutional and low-density parity checks coding. The proposed scheme provides an attractive low-complexity alternative to iterative receivers based on state-space models for channel parameter evolution. The use of pilot symbols is demonstrated to aid the equalizer both directly through channel estimation and indirectly through pilot message insertion.

A (64,45) Triple Error Correction Code for Memory Applications

Memories are commonly protected with error correction codes to avoid data corruption when a soft error occurs. Traditionally, per-word single error correction (SEC) codes are used. This is because they are simple to implement and provide low latency. More advanced codes have been considered, but their main drawback is the complexity of the decoders and the added latency. Recently, the use of one-step majority logic decodable codes has been proposed for memory protection. One-step majority logic decoding enables the use of low-complexity decoders, and low latency can also be achieved with moderate complexity. The main issue is that there are only a few codes that are one-step majority logic decodable. This restricts the choice of word lengths and error correction capabilities. In this paper, a method to derive new codes from a class of one-step majority logic decodable codes known as difference-set codes is proposed. The derived codes can also be efficiently implemented. As an example, a (64,45) triple error correction (TEC) code is derived and compared with existing SEC and TEC codes. The results presented enable a wider choice of word lengths and error correction capabilities that will be useful for memory designs.

Multiple Cell Upset Correction in Memories Using Difference Set Codes

Error Correction Codes (ECCs) are commonly used to protect memories from soft errors. As technology scales, Multiple Cell Upsets (MCUs) become more common and affect a larger number of cells. An option to protect memories against MCUs is to use advanced ECCs that can correct more than one error per word. In this area, the use of one step majority logic decodable codes has recently been proposed for memory applications. Difference Set (DS) codes are one example of these codes. In this paper, a scheme is presented to protect a memory from MCUs using Difference Set codes. The proposed scheme exploits the localization of the errors in an MCU, as well as the properties of DS codes, to provide enhanced error correction capabilities. The properties of the DS codes are also used to reduce the decoding time. The scheme has been implemented in HDL, and circuit area and speed estimates are provided.

On the growth rate of the weight distribution of irregular doubly-generalized LDPC codes

In this paper, the asymptotic growth rate of the weight distribution of irregular doubly generalized LDPC (D-GLDPC) codes is derived. The analysis yields a compact expression which accurately approximates the growth rate function for the case of small linear-weight codewords. This paper generalizes existing results for LDPC and generalized LDPC (GLDPC) codes. Ensembles with smallest check or variable node minimum distance greater than 2 are shown to have good growth-rate behavior, while for other ensembles a fundamental parameter is identified which discriminates between an asymptotically small and an asymptotically large expected number of small linear-weight codewords. Also, in the latter case it is shown that the growth rate depends only on the check and variable nodes with minimum distance 2. An important connection between this new result and the stability condition of D-GLDPC codes over the BEC is highlighted. Such a connection, previously observed for LDPC and GLDPC codes, is now extended to the case of D-GLDPC codes. Finally, it is shown that the analysis may be extended to include the growth rate of the stopping set size distribution of irregular D-GLDPC codes.

On the Pseudocodeword Redundancy of Binary Linear Codes

For a binary linear code, the pseudocodeword redundancy with respect to the additive white Gaussian noise channel, the binary symmetric channel, or the max-fractional weight is defined to be the smallest number of rows in a parity-check matrix such that the corresponding minimum pseudoweight is equal to the minimum Hamming distance of the code. It is shown that most codes do not have a finite pseudocodeword redundancy. Also, upper bounds on the pseudocodeword redundancy for some families of codes, including codes based on designs, are provided. The pseudocodeword redundancies for all codes of small length (at most 9) are computed. Furthermore, comprehensive results are provided on the cases of cyclic codes of length at most 250 for which the eigenvalue bound of Vontobel and Koetter is sharp.

A Soft Decode–Compress–Forward Relaying Scheme for Cooperative Wireless Networks

This paper proposes a new technique for soft information relaying, which is based on a soft decode-compress-forward relay protocol. The proposed system provides a means of using distributed low-density parity-check (LDPC) coding in conjunction with higher order modulation, such as pulse amplitude modulation (PAM) and quadrature amplitude modulation (QAM), which is effective even under poor source-relay link conditions. Ordinarily, such schemes suffer from error propagation to the destination caused by incorrect decoding at the relay when the signal-to-noise ratio (SNR) on the source-relay link is low; however, our system avoids this problem by generating soft versions of the additional (parity-bearing) PAM symbols for transmission from the relay. The proposed technique of soft compression does not suffer from parity log-likelihood ratios (LLRs) converging to zero, as do many soft re-encoding techniques for turbo and LDPC codes. In the case of Gray-coded PAM/QAM signaling, we also propose a method of performing exact expectation-based soft modulation with low computational complexity. Furthermore, we propose a new model, which we refer to as the soft scalar model, for the overall source-to-destination channel encountered by the constellation symbols, and this model is used at the destination to compute LLRs for joint decoding of the distributed LDPC code. Simulation results demonstrate that the proposed scheme can provide good coding gain, diversity gain, and spectral efficiency under poor source-relay SNR conditions.

LDPC coding with soft information relaying in cooperative wireless networks

This paper investigates soft information relaying (SIR) for low-density parity-check (LDPC) coded transmission in wireless networks. We introduce a new scheme for soft parity symbol generation at the relay, which features two key strategies: a two-step soft parity generation process, and a prescaling technique. The two-step soft parity generation procedure is designed to allow efficient relay processing, while yielding an overall (i.e., destination) parity-check matrix structure with desirable properties. The pre-scaling method prevents the amplitudes of generated soft symbols successively converging to zero, as happens with some existing soft forwarding methods. Finally, we propose an appropriate LLR former at the destination which is tailored to the proposed soft parity generation technique. Simulation results demonstrate that the proposed relay protocol yields an improved BER performance compared to competitive schemes proposed in the literature.