Mark G. Johnson

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

This paper describes clock recovery circuits specifically designed for the hostile noise environment found aboard dynamic RAM chips. Instead of a phase-locked loop having a voltage-controlled oscillator, these circuits implement a delay-locked loop, thereby achieving low jitter and reduced sensitivity to noise on the substrate and the power supply rails. Differential signals are employed both in signal paths and in control paths, further decreasing noise sensitivity and simultaneously allowing operation from low voltage supplies. An unorthodox voltage controlled phase shifter, operating on the principle of quadrature mixing, yields a circuit with unlimited delay range (modulo 2/spl pi/ radians). Minor loops, enclosed within the overall loop feedback path, perform active duty cycle correction. Measured results show peak-to-peak jitter of 140 ps on the internal clock signal, and 250 ps on the external data pins, sufficiently small to allow 500 Megabyte/s transfer rates at the I/O interface. >

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-/spl mu/m CMOS substrate. One-time programming is performed by applying a high voltage across the cell terminals, which ruptures the antifuse and permanently encodes a logic 0. Unruptured antifuses encode a logic 1. Cells are arranged in 8-Mb tiles, 1 K rows by 1 K columns by 8 bits high. The die contains 72 such tiles: 64 tiles for data and eight tiles for error-correcting code bits. Wordline and bitline decoders, bias circuits, and sense amplifiers are built in the CMOS substrate directly beneath the memory tiles, improving die efficiency. The device supports a generic standard NAND flash interface and operates from a single 3.3-V supply.

512 Mb PROM with 8 layers of antifuse/diode cells

A 3.3 V, 512 Mb PROM uses a transistorless memory cell containing an antifuse and diode. A bit area of 1.4F/sup 2/ including all overhead is achieved by stacking cells 8 high above the 0.25 /spl mu/m CMOS substrate. Read bandwidth is 1 MB/s and write bandwidth is 0.5 MB/s. A 72 b Hamming code provides fault tolerance.

A 660 MB/s interface megacell portable circuit in 0.3 /spl mu/m-0.7 /spl mu/m CMOS ASIC

A high-speed interface circuit delivering 660 MB/s data is implemented as a byte-wide I/O bus-interface cell. The interface contains low-swing input receivers, controlled-current output drivers, and clock-recovery circuits. The circuits perform well in noisy environments such as microprocessors, and withstand LdI/dt noise generated in high-inductance packages such as PQFPs. The interface is implemented as a full-custom ASIC library mega-cell, reducing area and power over gate-array approaches. An advanced CAD methodology is used to easily port the analog circuits and high-speed digital circuits in the interface cell to multiple-fabrication process technologies. The cell is used as an interface for ASIC-to-DRAM communication and for ASIC-to-ASIC communication, for point-to-point links and for bused links.

An input-free V/sub T/ extractor circuit using a two-transistor differential amplifier

A three-terminal circuit (power, ground, and output) that provides a DC output voltage equal to the MOS threshold voltage V/sub T/ is presented. The circuit uses the four-terminal extractor topology of Z. Wang (1992), but it adds self-biasing and a two-transistor differential amplifier to provide a ground-referenced output voltage. >

Circuit techniques in a 266-MHz MMX-enabled processor

The AMD-K6 MMX-enabled processor is plug-compatible with the industry-standard Socket 7 and is binary compatible with the existing base of legacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution. High performance and compact die size are achieved by using self-resetting, self-timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells. The 162 sq. mm die is fabricated on a 0.35-/spl mu/m, five-layer metal process with local interconnect. It is assembled into a ceramic pin grid array (PGA) using C4 flip-chip mounting. The processor functions at clock speeds up to 266 MHz.

An X86 microprocessor with multimedia extensions

This sixth-generation X86 instruction-set compatible microprocessor implements a set of multimedia extensions. Instruction predecoding to identify instruction boundaries begins during filling of the 32 kB two-way set associative instruction cache after which the predecode bits are stored in the 20 kB predecode cache. The processor decodes up to two X86 instructions per clock, most of which are decoded by hardware into one to four RISC-like operations, called RISC86 Ops, whereas the uncommon instructions are mapped into ROM-resident RISC sequences. The instruction scheduler buffers up to 24 RISC86 operations, using register renaming with a total of 48 registers. Up to six RISC86 instructions are issued out-of-order to seven parallel execution units, speculatively executed and retired in order. The branch algorithm uses two-level branch prediction based on an 8192-entry branch history table, a 16-entry branch target cache and a 16-entry return address stack. The 10.18/spl times/15.38 mm/sup 2/ die contains 8.8M transistors. The chip is in 0.35 /spl mu/m CMOS using five layers of metal, shallow trench isolation, and tungsten local interconnect.

A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM

This paper describes a pair of delay-locked loops (one DLL for transmitting data, one for receiving) that satisfy the requirement for accurate timing (sub-100ps static phase error), even in the noisy environment (substrate and V/sub DD/) of DRAMs, to allow data transfer rates exceeding 500Mb/s/pin at 2.5V. While the application of delay-locked loops to the problem of host-slave synchronization is not new, the loop described in this paper solves several problems of conventional PLLs and DLLs, providing unlimited phase shift (modulo 2/spl pi/) without a VCO, enabling lock in under 200ns and good jitter performance at low supply voltages.<<ETX>>