Mark-Jan Spijkman

Dual-Gate Thin-Film Transistors, Integrated Circuits and Sensors

The first dual-gate thin-film transistor (DGTFT) was reported in 1981 with CdSe as the semiconductor. Other TFT technologies such as a-Si:H and organic semiconductors have led to additional ways of making DGTFTs. DGTFTs contain a second gate dielectric with a second gate positioned opposite of the first gate. The main advantage is that the threshold voltage can be set as a function of the applied second gate bias. The shift depends on the ratio of the capacitances of the two gate dielectrics. Here we review the fast growing field of DGTFTs. We summarize the reported operational mechanisms, and the application in logic gates and integrated circuits. The second emerging application of DGTFTs is sensitivity enhancement of existing ion-sensitive field-effect transistors (ISFET). The reported sensing mechanism is discussed and an outlook is presented.

Revealing Buried Interfaces to Understand the Origins of Threshold Voltage Shifts in Organic Field‐Effect Transistors

The semiconductor of an organic field-effect transistor is stripped with adhesive tape, yielding an exposed gate dielectric, accessible for various characterization techniques. By using scanning Kelvin probe microscopy we reveal that trapped charges after gate bias stress are located at the gate dielectric and not in the semiconductor. Charging of the gate dielectric is confirmed by the fact that the threshold voltage shift remains, when a pristine organic semiconductor is deposited on the exposed gate dielectric of a stressed and delaminated field-effect transistor.

Beyond the Nernst-limit with dual-gate ZnO ion-sensitive field-effect transistors

The sensitivity of conventional ion-sensitive field-effect transistors (ISFETs) is limited to 59 mV/pH, which is the maximum detectable change in electrochemical potential according to the Nernst equation. Here we demonstrate a transducer based on a ZnO dual-gate field-effect transistor that breaches this boundary. To enhance the response to the pH of the electrolyte, a self-assembled monolayer has been used as a top gate dielectric. The sensitivity scales linearly with the ratio between the top and bottom gate capacitances. The sensitivity of our ZnO ISFET of 22 mV/pH is enhanced by more than two orders of magnitude up to 2.25 V/pH.

DNA adsorption measured with ultra-thin film organic field effect transistors

Organic ultra-thin film field effect transistors (FET) are operated as label-free sensors of deoxyribonucleic acid (DNA) adsorption. Linearized plasmid DNA molecules (4361 base pairs) are deposited from a solution on two monolayers thick pentacene FET. The amount of adsorbed DNA is measured by AFM and correlated to the concentration of the solution. Electrical characteristics on the dried DNA/pentacene FETs were studied as a function of DNA concentration in the solution. Shift of the pinch-off voltage across a wide range of DNA concentration, from very diluted to highly concentrated, is observed. It can be ascribed to additional positive charges in the semiconductor induced by DNA at a rate of one charge for every 200 base pairs. The sensitivity 74 ng/cm(2), corresponding to 650 ng/ml, is limited by the distribution of FET parameters upon repeated cycles, and is subjected to substantial improvement upon standardization. Our work demonstrates the possibility to develop label-free transducers suitable to operate in regimes of high molecular entanglement.

Increasing the noise margin in organic circuits using dual gate field-effect transistors

Complex digital circuits reliably work when the noise margin of the logic gates is sufficiently high. For p-type only inverters, the noise margin is typically about 1 V. To increase the noise margin, we fabricated inverters with dual gate transistors. The top gate is advantageously used to independently tune the threshold voltage.

Charge transport in dual-gate organic field-effect transistors

The charge carrier distribution in dual-gate field-effect transistors is investigated as a function of semiconductor thickness. A good agreement with 2-dimensional numerically calculated transfer curves is obtained. For semiconductor thicknesses larger than the accumulation width, two spatially separated channels are formed. The cross-over from accumulation into depletion of the two channels in combination with a carrier density dependent mobility causes a shoulder in the transfer characteristics. A semiconducting monolayer has only a single channel. The charge carrier density, and consequently the mobility, are virtually constant and change monotonically with applied gate biases, leading to transfer curves without a shoulder.

Monolayer dual gate transistors with a single charge transport layer

A dual gate transistor was fabricated using a self-assembled monolayer as the semiconductor. We show the possibility of processing a dielectric on top of the self-assembled monolayer without deteriorating the device performance. The two gates of the transistor accumulate charges in the monomolecular transport layer and artifacts caused by the semiconductor thickness are negated. We investigate the electrical transport in a dual gate self-assembled monolayer field-effect transistor and present a detailed analysis of the importance of the contact geometry in monolayer field-effect transistors.

Controlling the on/off current ratio of ferroelectric field-effect transistors

The on/off current ratio in organic ferroelectric field-effect transistors (FeFETs) is largely determined by the position of the threshold voltage, the value of which can show large device-to-device variations. Here we show that by employing a dual-gate layout for the FeFET, we can gain full control over the on/off ratio. In the resulting dual-gate FeFET the ferroelectric gate provides the memory functionality and the second, non-ferroelectric, control gate is advantageously used to set the threshold voltage. The on/off ratio can thus be maximized at the readout bias. The operation is explained by the quantitative analysis of charge transport in a dual-gate FeFET.